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[54/61] phb4: Cleanup PEC config discovery in CAPI mode

Message ID 20210719132012.150948-55-hegdevasant@linux.vnet.ibm.com
State Superseded
Headers show
Series P10 Enablement | expand

Commit Message

Vasant Hegde July 19, 2021, 1:20 p.m. UTC
From: Frederic Barrat <fbarrat@linux.ibm.com>

Small cleanup when reading the PEC config when setting up CAPI, in
preparation for P10. Scom addresses vary between P9 and P10 and we'll
be accessing more than one PCI chiplet. No functional change.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
 hw/phb4.c           | 17 +++++++++--------
 include/phb4-regs.h | 10 +++++++---
 2 files changed, 16 insertions(+), 11 deletions(-)
diff mbox series

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index e3cf9038e..274fa356a 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -4282,7 +4282,7 @@  static int64_t phb4_get_capp_info(int chip_id, struct phb *phb,
 
 static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 {
-	uint64_t reg;
+	uint64_t addr, reg;
 	uint32_t offset;
 	uint8_t link_width_x16 = 1;
 
@@ -4293,9 +4293,10 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 		/* Check if PEC2 is in x8 or x16 mode.
 		 * PEC0 is always in x16
 		 */
-		xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, &reg);
-		link_width_x16 = ((reg & XPEC_PCI2_IOVALID_MASK) ==
-				  XPEC_PCI2_IOVALID_X16);
+		addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET;
+		xscom_read(p->chip_id, addr, &reg);
+		link_width_x16 = ((reg & XPEC_P9_PCI_IOVALID_MASK) ==
+				  XPEC_P9_PCI_IOVALID_X16);
 	}
 
 	/* APC Master PowerBus Control Register */
@@ -4515,7 +4516,7 @@  static void phb4_init_capp_errors(struct phb4 *p)
 static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 				uint32_t capp_eng)
 {
-	uint64_t reg, start_addr, end_addr, stq_eng, dma_eng;
+	uint64_t addr, reg, start_addr, end_addr, stq_eng, dma_eng;
 	uint64_t mbt0, mbt1;
 	int i, window_num = -1;
 
@@ -4553,9 +4554,9 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 
 	if (p->index == CAPP1_PHB_INDEX) {
 		/* Check if PEC is in x8 or x16 mode */
-		xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, &reg);
-
-		if ((reg & XPEC_PCI2_IOVALID_MASK) == XPEC_PCI2_IOVALID_X16) {
+		addr = XPEC_P9_PCI_CPLT_CONF1 + 2 * XPEC_PCI_CPLT_OFFSET;
+		xscom_read(p->chip_id, addr, &reg);
+		if ((reg & XPEC_P9_PCI_IOVALID_MASK) == XPEC_P9_PCI_IOVALID_X16) {
 			/* PBCQ is operating as a x16 stack
 			 * - The maximum number of engines give to CAPP will be
 			 * 14 and will be assigned in the order of STQ 15 to 2.
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 85d2cf2ea..b4a94c056 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -385,9 +385,13 @@ 
 
 
 /* PCI Chiplet Config Register */
-#define XPEC_PCI2_CPLT_CONF1			0x000000000F000009ULL
-#define XPEC_PCI2_IOVALID_MASK			PPC_BITMASK(4, 6)
-#define XPEC_PCI2_IOVALID_X16			PPC_BIT(4)
+#define XPEC_PCI_CPLT_OFFSET			0x1000000ULL
+#define XPEC_P9_PCI_CPLT_CONF1			0x000000000D000009ULL
+#define   XPEC_P9_PCI_IOVALID_MASK		PPC_BITMASK(4, 6)
+#define   XPEC_P9_PCI_IOVALID_X16		PPC_BIT(4)
+#define   XPEC_P9_PCI_LANE_CFG			PPC_BITMASK(10, 11)
+#define XPEC_P10_PCI_CPLT_CONF1			0x0000000008000009ULL
+#define   XPEC_P10_PCI_LANE_CFG			PPC_BITMASK(0, 1)
 
 /*
  * IODA3 on-chip tables