diff mbox series

[19/61] hdata/iohub: Read PCI Gen5 equalization settings for P10

Message ID 20210719132012.150948-20-hegdevasant@linux.vnet.ibm.com
State Superseded
Headers show
Series P10 Enablement | expand

Commit Message

Vasant Hegde July 19, 2021, 1:19 p.m. UTC 
From: Frederic Barrat <fbarrat@linux.ibm.com>

HDAT spec added fields to define the equalization settings for PCI
Gen5 link. Format is the same as PCI Gen4, so we just need to add
extra fields in the "ibm,lane-eq" in the device tree.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
 hdata/iohub.c | 27 ++++++++++++++++++---------
 hdata/spira.h |  8 +++++++-
 2 files changed, 25 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/hdata/iohub.c b/hdata/iohub.c
index fb215e1fb..92df48b8f 100644
--- a/hdata/iohub.c
+++ b/hdata/iohub.c
@@ -152,8 +152,8 @@  static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub,
 {
 	struct dt_node *stack;
 	const char *compat;
-	u64 eq[8];
-	u8 *gen4;
+	u64 eq[12];
+	u8 *ptr;
 	int i;
 
 	stack = dt_new_addr(pbcq, "stack", stack_index);
@@ -181,18 +181,27 @@  static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub,
 		eq[i] = be64_to_cpu(hub->phb_lane_eq[phb_index][i]);
 	for (i = 0; i < 4; i++) /* gen 4 eq settings */
 		eq[i+4] = be64_to_cpu(hub->phb4_lane_eq[phb_index][i]);
+	for (i = 0; i < 4; i++) /* gen 5 eq settings */
+		eq[i+8] = be64_to_cpu(hub->phb5_lane_eq[phb_index][i]);
 
 	/* Lane-eq settings are packed 2 bytes per lane for 16 lanes
-	 * On P9 DD2, 1 byte  per lane is  used in the hardware
+	 * On P9 DD2 and P10, 1 byte per lane is used in the hardware
 	 */
 
-	/* Repack 2 byte lane settings into 1 byte */
-	gen4 = (u8 *)&eq[4];
-	for (i = 0; i < 16; i++)
-		gen4[i] = gen4[2*i];
+	/* Repack 2 byte lane settings into 1 byte for gen 4 & 5 */
+	ptr = (u8 *)&eq[4];
+	for (i = 0; i < 32; i++)
+		ptr[i] = ptr[2*i];
 
-	dt_add_property_u64s(stack, "ibm,lane-eq", eq[0], eq[1],
-			     eq[2], eq[3], eq[4], eq[5]);
+	if (proc_gen == proc_gen_p9)
+		dt_add_property_u64s(stack, "ibm,lane-eq",
+				     eq[0], eq[1], eq[2], eq[3],
+				     eq[4], eq[5]);
+	else
+		dt_add_property_u64s(stack, "ibm,lane-eq",
+				     eq[0], eq[1], eq[2], eq[3],
+				     eq[4], eq[5],
+				     eq[6], eq[7]);
 	return stack;
 }
 
diff --git a/hdata/spira.h b/hdata/spira.h
index 3a8a31e1a..7fcf5c302 100644
--- a/hdata/spira.h
+++ b/hdata/spira.h
@@ -706,8 +706,11 @@  struct cechub_io_hub {
 		/* HDAT >= v9.x, HDIF version 0x6A adds phb_lane_eq with four
 		 *               words per PHB (4 PHBs).
 		 *
-		 * HDAT >= 10.x, HDIF version 0x7A adds space for another two
+		 * HDAT >= 10.x, HDIF version 0x7A adds space for another
 		 *               two PHBs (6 total) and the gen4 EQ values.
+		 *
+		 * HDAT >= 10.5x, HDIF version 0x8B adds space for the
+		 *                gen5 EQ values.
 		 */
 		struct {
 			/* Gen 3 PHB eq values, 6 PHBs */
@@ -715,6 +718,9 @@  struct cechub_io_hub {
 
 			/* Gen 4 PHB eq values */
 			__be64		phb4_lane_eq[6][4];
+
+			/* Gen 5 PHB eq values */
+			__be64		phb5_lane_eq[6][4];
 		};
 	};
 } __packed;