| Message ID | 20230329172903.636383-20-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | remove MISA ext_N flags from cpu->cfg, | expand |
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it > the same way we did with the others: create a "g" RISCVCPUMisaExtConfig > property, remove the old "g" property, remove all instances of 'cfg.ext_g' > and use riscv_has_ext(env, RVG). > > The caveat is that we don't have RVG, so add it. RVG will be used right > off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is > enabling G via the now removed 'ext_g' flag. > > After this patch, there are no more MISA extensions represented by flags > in RISCVCPUConfig. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 17 ++++++++--------- > target/riscv/cpu.h | 2 +- > 2 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 036d6191ca..6988ff443a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -396,10 +396,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > RISCVCPU *cpu = RISCV_CPU(obj); > > - set_misa(env, MXL_RV64, RVC | RVS | RVU); > + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_11_0); > > - cpu->cfg.ext_g = true; > cpu->cfg.ext_zfh = true; > cpu->cfg.mmu = true; > cpu->cfg.ext_xtheadba = true; > @@ -807,12 +806,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > CPURISCVState *env = &cpu->env; > > /* Do some ISA extension error checking */ > - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && > - riscv_has_ext(env, RVM) && > - riscv_has_ext(env, RVA) && > - riscv_has_ext(env, RVF) && > - riscv_has_ext(env, RVD) && > - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > + if (riscv_has_ext(env, RVG) && > + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && > + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && > + riscv_has_ext(env, RVD) && > + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > cpu->cfg.ext_icsr = true; > cpu->cfg.ext_ifencei = true; > @@ -1402,6 +1400,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > .misa_bit = RVJ, .enabled = false}, > {.name = "v", .description = "Vector operations", > .misa_bit = RVV, .enabled = false}, > + {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", > + .misa_bit = RVG, .enabled = false}, > }; > > static void riscv_cpu_add_misa_properties(Object *cpu_obj) > @@ -1424,7 +1424,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) > > static Property riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), > DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c0280ace2a..ce92e8393d 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -81,6 +81,7 @@ > #define RVU RV('U') > #define RVH RV('H') > #define RVJ RV('J') > +#define RVG RV('G') > > > /* Privileged specification version */ > @@ -418,7 +419,6 @@ typedef struct { > } RISCVSATPMap; > > struct RISCVCPUConfig { > - bool ext_g; > bool ext_zba; > bool ext_zbb; > bool ext_zbc; > -- > 2.39.2 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 036d6191ca..6988ff443a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -396,10 +396,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - set_misa(env, MXL_RV64, RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); - cpu->cfg.ext_g = true; cpu->cfg.ext_zfh = true; cpu->cfg.mmu = true; cpu->cfg.ext_xtheadba = true; @@ -807,12 +806,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) CPURISCVState *env = &cpu->env; /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && - riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && - riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_icsr = true; cpu->cfg.ext_ifencei = true; @@ -1402,6 +1400,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVJ, .enabled = false}, {.name = "v", .description = "Vector operations", .misa_bit = RVV, .enabled = false}, + {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", + .misa_bit = RVG, .enabled = false}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1424,7 +1424,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0280ace2a..ce92e8393d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') /* Privileged specification version */ @@ -418,7 +419,6 @@ typedef struct { } RISCVSATPMap; struct RISCVCPUConfig { - bool ext_g; bool ext_zba; bool ext_zbb; bool ext_zbc;