| Message ID | 20230329172903.636383-15-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | remove MISA ext_N flags from cpu->cfg, | expand |
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Create a new "h" RISCVCPUMisaExtConfig property that will update > env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are > replaced with riscv_has_ext(env, RVH). > > Remove the old "h" property and 'ext_h' from RISCVCPUConfig. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 10 +++++----- > target/riscv/cpu.h | 1 - > 2 files changed, 5 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a72bc651cf..76dcf26f6c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -840,13 +840,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { > + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { > error_setg(errp, > "H depends on an I base integer ISA with 32 x registers"); > return; > } > > - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { > + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { > error_setg(errp, "H extension implicitly requires S-mode"); > return; > } > @@ -1112,7 +1112,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) > if (riscv_has_ext(env, RVU)) { > ext |= RVU; > } > - if (riscv_cpu_cfg(env)->ext_h) { > + if (riscv_has_ext(env, RVH)) { > ext |= RVH; > } > if (riscv_cpu_cfg(env)->ext_v) { > @@ -1449,6 +1449,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > .misa_bit = RVS, .enabled = true}, > {.name = "u", .description = "User-level instructions", > .misa_bit = RVU, .enabled = true}, > + {.name = "h", .description = "Hypervisor", > + .misa_bit = RVH, .enabled = true}, > }; > > static void riscv_cpu_add_misa_properties(Object *cpu_obj) > @@ -1473,7 +1475,6 @@ static Property riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), > DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), > DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > @@ -1578,7 +1579,6 @@ static void register_cpu_props(Object *obj) > */ > if (cpu->env.misa_ext != 0) { > cpu->cfg.ext_v = misa_ext & RVV; > - cpu->cfg.ext_h = misa_ext & RVH; > cpu->cfg.ext_j = misa_ext & RVJ; > > /* > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7b98cf4dd7..f3cb28443c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -419,7 +419,6 @@ typedef struct { > > struct RISCVCPUConfig { > bool ext_g; > - bool ext_h; > bool ext_j; > bool ext_v; > bool ext_zba; > -- > 2.39.2 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a72bc651cf..76dcf26f6c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -840,13 +840,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers"); return; } - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1112,7 +1112,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_has_ext(env, RVU)) { ext |= RVU; } - if (riscv_cpu_cfg(env)->ext_h) { + if (riscv_has_ext(env, RVH)) { ext |= RVH; } if (riscv_cpu_cfg(env)->ext_v) { @@ -1449,6 +1449,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVS, .enabled = true}, {.name = "u", .description = "User-level instructions", .misa_bit = RVU, .enabled = true}, + {.name = "h", .description = "Hypervisor", + .misa_bit = RVH, .enabled = true}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1473,7 +1475,6 @@ static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1578,7 +1579,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext != 0) { cpu->cfg.ext_v = misa_ext & RVV; - cpu->cfg.ext_h = misa_ext & RVH; cpu->cfg.ext_j = misa_ext & RVJ; /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7b98cf4dd7..f3cb28443c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { struct RISCVCPUConfig { bool ext_g; - bool ext_h; bool ext_j; bool ext_v; bool ext_zba;