mbox series

[v3,00/20] remove MISA ext_N flags from cpu->cfg,

Message ID 20230329172903.636383-1-dbarboza@ventanamicro.com
Headers show
Series remove MISA ext_N flags from cpu->cfg, | expand

Message

Daniel Henrique Barboza March 29, 2023, 5:28 p.m. UTC 
Hi,

This new version has a new patch (3) that removes the 'multi_letter'
attribute from isa_ext_data that became redundant after the changes made
in patch 2. The change was proposed by Weiwei Li in the v2.

All patches but patch 3 are acked.

Changes from v2:
- patch 3 (new)
  - remove 'multi_letter' from isa_ext_data
- v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06493.html

Daniel Henrique Barboza (20):
  target/riscv: sync env->misa_ext* with cpu->cfg in realize()
  target/riscv: remove MISA properties from isa_edata_arr[]
  target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
  target/riscv: introduce riscv_cpu_add_misa_properties()
  target/riscv: remove cpu->cfg.ext_a
  target/riscv: remove cpu->cfg.ext_c
  target/riscv: remove cpu->cfg.ext_d
  target/riscv: remove cpu->cfg.ext_f
  target/riscv: remove cpu->cfg.ext_i
  target/riscv: remove cpu->cfg.ext_e
  target/riscv: remove cpu->cfg.ext_m
  target/riscv: remove cpu->cfg.ext_s
  target/riscv: remove cpu->cfg.ext_u
  target/riscv: remove cpu->cfg.ext_h
  target/riscv: remove cpu->cfg.ext_j
  target/riscv: remove cpu->cfg.ext_v
  target/riscv: remove riscv_cpu_sync_misa_cfg()
  target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
  target/riscv: add RVG and remove cpu->cfg.ext_g
  target/riscv/cpu.c: redesign register_cpu_props()

 target/riscv/cpu.c | 386 +++++++++++++++++++++++----------------------
 target/riscv/cpu.h |  19 +--
 2 files changed, 202 insertions(+), 203 deletions(-)

Comments

Alistair Francis April 6, 2023, 12:32 a.m. UTC | #1 
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This new version has a new patch (3) that removes the 'multi_letter'
> attribute from isa_ext_data that became redundant after the changes made
> in patch 2. The change was proposed by Weiwei Li in the v2.
>
> All patches but patch 3 are acked.
>
> Changes from v2:
> - patch 3 (new)
>   - remove 'multi_letter' from isa_ext_data
> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06493.html
>
> Daniel Henrique Barboza (20):
>   target/riscv: sync env->misa_ext* with cpu->cfg in realize()
>   target/riscv: remove MISA properties from isa_edata_arr[]
>   target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
>   target/riscv: introduce riscv_cpu_add_misa_properties()
>   target/riscv: remove cpu->cfg.ext_a
>   target/riscv: remove cpu->cfg.ext_c
>   target/riscv: remove cpu->cfg.ext_d
>   target/riscv: remove cpu->cfg.ext_f
>   target/riscv: remove cpu->cfg.ext_i
>   target/riscv: remove cpu->cfg.ext_e
>   target/riscv: remove cpu->cfg.ext_m
>   target/riscv: remove cpu->cfg.ext_s
>   target/riscv: remove cpu->cfg.ext_u
>   target/riscv: remove cpu->cfg.ext_h
>   target/riscv: remove cpu->cfg.ext_j
>   target/riscv: remove cpu->cfg.ext_v
>   target/riscv: remove riscv_cpu_sync_misa_cfg()
>   target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
>   target/riscv: add RVG and remove cpu->cfg.ext_g
>   target/riscv/cpu.c: redesign register_cpu_props()

Thanks for the cleanup. Do you mind rebasing it on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next then I
will apply it

Alistair

>
>  target/riscv/cpu.c | 386 +++++++++++++++++++++++----------------------
>  target/riscv/cpu.h |  19 +--
>  2 files changed, 202 insertions(+), 203 deletions(-)
>
> --
> 2.39.2
>
>