| Message ID | 20220315065529.62198-3-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Initial support for the Sdtrig extension via M-mode CSRs | expand |
On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > Add a subsection to machine.c to migrate debug CSR state. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > > (no changes since v2) > > Changes in v2: > - new patch: add debug state description > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 5178b3fec9..4921dad09d 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static bool debug_needed(void *opaque) > +{ > + RISCVCPU *cpu = opaque; > + CPURISCVState *env = &cpu->env; > + > + return riscv_feature(env, RISCV_FEATURE_DEBUG); This fails to build: ../target/riscv/machine.c: In function ‘debug_needed’: ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ undeclared (first use in this function); did you mean ‘RISCV_FEATURE_EPMP’? 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); | ^~~~~~~~~~~~~~~~~~~ | RISCV_FEATURE_EPMP ../target/riscv/machine.c:228:31: note: each undeclared identifier is reported only once for each function it appears in ../target/riscv/machine.c:229:1: warning: control reaches end of non-void function [-Wreturn-type] 229 | } | ^ Alistair > +} > > +static const VMStateDescription vmstate_debug_type2 = { > + .name = "cpu/debug/type2", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINTTL(mcontrol, type2_trigger_t), > + VMSTATE_UINTTL(maddress, type2_trigger_t), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static const VMStateDescription vmstate_debug = { > + .name = "cpu/debug", > + .version_id = 1, > + .minimum_version_id = 1, > + .needed = debug_needed, > + .fields = (VMStateField[]) { > + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), > + VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM, > + 0, vmstate_debug_type2, type2_trigger_t), > VMSTATE_END_OF_LIST() > } > }; > @@ -292,6 +323,7 @@ const VMStateDescription vmstate_riscv_cpu = { > &vmstate_pointermasking, > &vmstate_rv128, > &vmstate_kvmtimer, > + &vmstate_debug, > NULL > } > }; > -- > 2.25.1 > >
On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote: > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > From: Bin Meng <bin.meng@windriver.com> > > > > Add a subsection to machine.c to migrate debug CSR state. > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > > > (no changes since v2) > > > > Changes in v2: > > - new patch: add debug state description > > > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > > 1 file changed, 32 insertions(+) > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > index 5178b3fec9..4921dad09d 100644 > > --- a/target/riscv/machine.c > > +++ b/target/riscv/machine.c > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static bool debug_needed(void *opaque) > > +{ > > + RISCVCPU *cpu = opaque; > > + CPURISCVState *env = &cpu->env; > > + > > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > > This fails to build: > > ../target/riscv/machine.c: In function ‘debug_needed’: > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ > undeclared (first use in this function); did you mean > ‘RISCV_FEATURE_EPMP’? > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); > | ^~~~~~~~~~~~~~~~~~~ > | RISCV_FEATURE_EPMP > ../target/riscv/machine.c:228:31: note: each undeclared identifier is > reported only once for each function it appears in > ../target/riscv/machine.c:229:1: warning: control reaches end of > non-void function [-Wreturn-type] > 229 | } > | ^ That's weird. Maybe it's out of sync or merge conflict? I will take a look. Regards, Bin
Hi Alistair, On Wed, Apr 20, 2022 at 3:33 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote: > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > From: Bin Meng <bin.meng@windriver.com> > > > > > > Add a subsection to machine.c to migrate debug CSR state. > > > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > --- > > > > > > (no changes since v2) > > > > > > Changes in v2: > > > - new patch: add debug state description > > > > > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > > > 1 file changed, 32 insertions(+) > > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > > index 5178b3fec9..4921dad09d 100644 > > > --- a/target/riscv/machine.c > > > +++ b/target/riscv/machine.c > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > > + VMSTATE_END_OF_LIST() > > > + } > > > +}; > > > + > > > +static bool debug_needed(void *opaque) > > > +{ > > > + RISCVCPU *cpu = opaque; > > > + CPURISCVState *env = &cpu->env; > > > + > > > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > This fails to build: > > > > ../target/riscv/machine.c: In function ‘debug_needed’: > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ > > undeclared (first use in this function); did you mean > > ‘RISCV_FEATURE_EPMP’? > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); > > | ^~~~~~~~~~~~~~~~~~~ > > | RISCV_FEATURE_EPMP > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is > > reported only once for each function it appears in > > ../target/riscv/machine.c:229:1: warning: control reaches end of > > non-void function [-Wreturn-type] > > 229 | } > > | ^ > > That's weird. Maybe it's out of sync or merge conflict? I will take a look. > I rebased the v4 series on top of your riscv-to-apply.next branch, indeed there is a merge conflict of target/riscv/machine.c. After I resolved the conflict, the build succeeded. I suspect you missed something during your handling of the merge conflict? Regards, Bin
On Wed, Apr 20, 2022 at 7:52 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Alistair, > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote: > > > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > From: Bin Meng <bin.meng@windriver.com> > > > > > > > > Add a subsection to machine.c to migrate debug CSR state. > > > > > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > --- > > > > > > > > (no changes since v2) > > > > > > > > Changes in v2: > > > > - new patch: add debug state description > > > > > > > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > > > > 1 file changed, 32 insertions(+) > > > > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > > > index 5178b3fec9..4921dad09d 100644 > > > > --- a/target/riscv/machine.c > > > > +++ b/target/riscv/machine.c > > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > > > + VMSTATE_END_OF_LIST() > > > > + } > > > > +}; > > > > + > > > > +static bool debug_needed(void *opaque) > > > > +{ > > > > + RISCVCPU *cpu = opaque; > > > > + CPURISCVState *env = &cpu->env; > > > > + > > > > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > > > This fails to build: > > > > > > ../target/riscv/machine.c: In function ‘debug_needed’: > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ > > > undeclared (first use in this function); did you mean > > > ‘RISCV_FEATURE_EPMP’? > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > | ^~~~~~~~~~~~~~~~~~~ > > > | RISCV_FEATURE_EPMP > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is > > > reported only once for each function it appears in > > > ../target/riscv/machine.c:229:1: warning: control reaches end of > > > non-void function [-Wreturn-type] > > > 229 | } > > > | ^ > > > > That's weird. Maybe it's out of sync or merge conflict? I will take a look. > > > > I rebased the v4 series on top of your riscv-to-apply.next branch, > indeed there is a merge conflict of target/riscv/machine.c. After I > resolved the conflict, the build succeeded. Looking at this patch series RISCV_FEATURE_DEBUG is only defined in patch 4, it doesn't currently exist in the tree. I'm not sure how this can build. Are you sure you looked at just this patch and not the entire series? > > I suspect you missed something during your handling of the merge conflict? That's entirely possible. Can you send a rebased version please Alistair > > Regards, > Bin
Hi Alistair, On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis <alistair23@gmail.com> wrote: > > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > Hi Alistair, > > > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote: > > > > > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > > > From: Bin Meng <bin.meng@windriver.com> > > > > > > > > > > Add a subsection to machine.c to migrate debug CSR state. > > > > > > > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > > --- > > > > > > > > > > (no changes since v2) > > > > > > > > > > Changes in v2: > > > > > - new patch: add debug state description > > > > > > > > > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > > > > > 1 file changed, 32 insertions(+) > > > > > > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > > > > index 5178b3fec9..4921dad09d 100644 > > > > > --- a/target/riscv/machine.c > > > > > +++ b/target/riscv/machine.c > > > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > > > > + VMSTATE_END_OF_LIST() > > > > > + } > > > > > +}; > > > > > + > > > > > +static bool debug_needed(void *opaque) > > > > > +{ > > > > > + RISCVCPU *cpu = opaque; > > > > > + CPURISCVState *env = &cpu->env; > > > > > + > > > > > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > > > > > This fails to build: > > > > > > > > ../target/riscv/machine.c: In function ‘debug_needed’: > > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ > > > > undeclared (first use in this function); did you mean > > > > ‘RISCV_FEATURE_EPMP’? > > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > | ^~~~~~~~~~~~~~~~~~~ > > > > | RISCV_FEATURE_EPMP > > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is > > > > reported only once for each function it appears in > > > > ../target/riscv/machine.c:229:1: warning: control reaches end of > > > > non-void function [-Wreturn-type] > > > > 229 | } > > > > | ^ > > > > > > That's weird. Maybe it's out of sync or merge conflict? I will take a look. > > > > > > > I rebased the v4 series on top of your riscv-to-apply.next branch, > > indeed there is a merge conflict of target/riscv/machine.c. After I > > resolved the conflict, the build succeeded. > > Looking at this patch series RISCV_FEATURE_DEBUG is only defined in > patch 4, it doesn't currently exist in the tree. I'm not sure how this > can build. Ah, it looks like I should adjust the patch order to have patch 4 come first. > > Are you sure you looked at just this patch and not the entire series? I see. I was looking at the series not this patch. It seems you were trying to build every commit for bisectabliity? Is there an easy way to do such automatically? > > > > > I suspect you missed something during your handling of the merge conflict? > > That's entirely possible. Can you send a rebased version please Regards, Bin
On Thu, Apr 21, 2022 at 9:47 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Alistair, > > On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis <alistair23@gmail.com> wrote: > > > > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > Hi Alistair, > > > > > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote: > > > > > > > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > > > > > From: Bin Meng <bin.meng@windriver.com> > > > > > > > > > > > > Add a subsection to machine.c to migrate debug CSR state. > > > > > > > > > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > > > --- > > > > > > > > > > > > (no changes since v2) > > > > > > > > > > > > Changes in v2: > > > > > > - new patch: add debug state description > > > > > > > > > > > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > > > > > > 1 file changed, 32 insertions(+) > > > > > > > > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > > > > > index 5178b3fec9..4921dad09d 100644 > > > > > > --- a/target/riscv/machine.c > > > > > > +++ b/target/riscv/machine.c > > > > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > > > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > > > > > + VMSTATE_END_OF_LIST() > > > > > > + } > > > > > > +}; > > > > > > + > > > > > > +static bool debug_needed(void *opaque) > > > > > > +{ > > > > > > + RISCVCPU *cpu = opaque; > > > > > > + CPURISCVState *env = &cpu->env; > > > > > > + > > > > > > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > > > > > > > This fails to build: > > > > > > > > > > ../target/riscv/machine.c: In function ‘debug_needed’: > > > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ > > > > > undeclared (first use in this function); did you mean > > > > > ‘RISCV_FEATURE_EPMP’? > > > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > > | ^~~~~~~~~~~~~~~~~~~ > > > > > | RISCV_FEATURE_EPMP > > > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is > > > > > reported only once for each function it appears in > > > > > ../target/riscv/machine.c:229:1: warning: control reaches end of > > > > > non-void function [-Wreturn-type] > > > > > 229 | } > > > > > | ^ > > > > > > > > That's weird. Maybe it's out of sync or merge conflict? I will take a look. > > > > > > > > > > I rebased the v4 series on top of your riscv-to-apply.next branch, > > > indeed there is a merge conflict of target/riscv/machine.c. After I > > > resolved the conflict, the build succeeded. > > > > Looking at this patch series RISCV_FEATURE_DEBUG is only defined in > > patch 4, it doesn't currently exist in the tree. I'm not sure how this > > can build. > > Ah, it looks like I should adjust the patch order to have patch 4 come first. > > > > > Are you sure you looked at just this patch and not the entire series? > > I see. I was looking at the series not this patch. > > It seems you were trying to build every commit for bisectabliity? Is > there an easy way to do such automatically? Yep, I build test every patch. I do this automatically with an internal Jenkins server, unfortunately I can't really share it publically Alistair > > > > > > > > > I suspect you missed something during your handling of the merge conflict? > > > > That's entirely possible. Can you send a rebased version please > > Regards, > Bin
On Thu, Apr 21, 2022 at 8:14 AM Alistair Francis <alistair23@gmail.com> wrote: > > On Thu, Apr 21, 2022 at 9:47 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > Hi Alistair, > > > > On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis <alistair23@gmail.com> wrote: > > > > > > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > Hi Alistair, > > > > > > > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote: > > > > > > > > > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > > > > > > > From: Bin Meng <bin.meng@windriver.com> > > > > > > > > > > > > > > Add a subsection to machine.c to migrate debug CSR state. > > > > > > > > > > > > > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > > > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > > > > --- > > > > > > > > > > > > > > (no changes since v2) > > > > > > > > > > > > > > Changes in v2: > > > > > > > - new patch: add debug state description > > > > > > > > > > > > > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > > > > > > > 1 file changed, 32 insertions(+) > > > > > > > > > > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > > > > > > index 5178b3fec9..4921dad09d 100644 > > > > > > > --- a/target/riscv/machine.c > > > > > > > +++ b/target/riscv/machine.c > > > > > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { > > > > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > > > > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > > > > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > > > > > > > + VMSTATE_END_OF_LIST() > > > > > > > + } > > > > > > > +}; > > > > > > > + > > > > > > > +static bool debug_needed(void *opaque) > > > > > > > +{ > > > > > > > + RISCVCPU *cpu = opaque; > > > > > > > + CPURISCVState *env = &cpu->env; > > > > > > > + > > > > > > > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > > > > > > > > > This fails to build: > > > > > > > > > > > > ../target/riscv/machine.c: In function ‘debug_needed’: > > > > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’ > > > > > > undeclared (first use in this function); did you mean > > > > > > ‘RISCV_FEATURE_EPMP’? > > > > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); > > > > > > | ^~~~~~~~~~~~~~~~~~~ > > > > > > | RISCV_FEATURE_EPMP > > > > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is > > > > > > reported only once for each function it appears in > > > > > > ../target/riscv/machine.c:229:1: warning: control reaches end of > > > > > > non-void function [-Wreturn-type] > > > > > > 229 | } > > > > > > | ^ > > > > > > > > > > That's weird. Maybe it's out of sync or merge conflict? I will take a look. > > > > > > > > > > > > > I rebased the v4 series on top of your riscv-to-apply.next branch, > > > > indeed there is a merge conflict of target/riscv/machine.c. After I > > > > resolved the conflict, the build succeeded. > > > > > > Looking at this patch series RISCV_FEATURE_DEBUG is only defined in > > > patch 4, it doesn't currently exist in the tree. I'm not sure how this > > > can build. > > > > Ah, it looks like I should adjust the patch order to have patch 4 come first. > > > > > > > > Are you sure you looked at just this patch and not the entire series? > > > > I see. I was looking at the series not this patch. > > > > It seems you were trying to build every commit for bisectabliity? Is > > there an easy way to do such automatically? > > Yep, I build test every patch. > > I do this automatically with an internal Jenkins server, unfortunately > I can't really share it publically > Okay, I will send a rebased version, plus fixing the patch order. Regards, Bin
On 4/20/22 16:46, Bin Meng wrote: > It seems you were trying to build every commit for bisectabliity? Is > there an easy way to do such automatically? git rebase --exec "cd build && make" r~
On Thu, Apr 21, 2022 at 11:51 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 4/20/22 16:46, Bin Meng wrote: > > It seems you were trying to build every commit for bisectabliity? Is > > there an easy way to do such automatically? > > git rebase --exec "cd build && make" > This works! Thanks Richard. Regards, Bin
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 5178b3fec9..4921dad09d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool debug_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_DEBUG); +} +static const VMStateDescription vmstate_debug_type2 = { + .name = "cpu/debug/type2", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(mcontrol, type2_trigger_t), + VMSTATE_UINTTL(maddress, type2_trigger_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_debug = { + .name = "cpu/debug", + .version_id = 1, + .minimum_version_id = 1, + .needed = debug_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), + VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM, + 0, vmstate_debug_type2, type2_trigger_t), VMSTATE_END_OF_LIST() } }; @@ -292,6 +323,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_debug, NULL } };