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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:55:42 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension Date: Tue, 15 Mar 2022 14:55:23 +0800 Message-Id: <20220315065529.62198-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds initial support for the Sdtrig extension via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is 2, which is the number that we can find in the SiFive U54/U74 cores. [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v4: - mention Sdtrig extension in the commit - rename 'struct trigger_type2_t' to 'type2_trigger_t' Changes in v3: - drop riscv_trigger_init(), which will be moved to patch #5 target/riscv/cpu.h | 5 + target/riscv/debug.h | 108 +++++++++++++ target/riscv/debug.c | 339 +++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 4 files changed, 453 insertions(+) create mode 100644 target/riscv/debug.h create mode 100644 target/riscv/debug.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa..ad35129239 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -102,6 +102,7 @@ typedef struct CPUArchState CPURISCVState; #if !defined(CONFIG_USER_ONLY) #include "pmp.h" +#include "debug.h" #endif #define RV_VLEN_MAX 1024 @@ -267,6 +268,10 @@ struct CPUArchState { pmp_table_t pmp_state; target_ulong mseccfg; + /* trigger module */ + target_ulong trigger_cur; + type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; + /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(uint32_t); uint32_t rdtime_fn_arg; diff --git a/target/riscv/debug.h b/target/riscv/debug.h new file mode 100644 index 0000000000..fbc5f946e2 --- /dev/null +++ b/target/riscv/debug.h @@ -0,0 +1,108 @@ +/* + * QEMU RISC-V Native Debug Support + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef RISCV_DEBUG_H +#define RISCV_DEBUG_H + +/* trigger indexes implemented */ +enum { + TRIGGER_TYPE2_IDX_0 = 0, + TRIGGER_TYPE2_IDX_1, + TRIGGER_TYPE2_NUM, + TRIGGER_NUM = TRIGGER_TYPE2_NUM +}; + +/* register index of tdata CSRs */ +enum { + TDATA1 = 0, + TDATA2, + TDATA3, + TDATA_NUM +}; + +typedef enum { + TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */ + TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */ + TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */ + TRIGGER_TYPE_INT = 4, /* interrupt trigger */ + TRIGGER_TYPE_EXCP = 5, /* exception trigger */ + TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */ + TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */ + TRIGGER_TYPE_UNAVAIL = 15 /* trigger exists, but unavailable */ +} trigger_type_t; + +typedef struct { + target_ulong mcontrol; + target_ulong maddress; + struct CPUBreakpoint *bp; + struct CPUWatchpoint *wp; +} type2_trigger_t; + +/* tdata field masks */ + +#define RV32_TYPE(t) ((uint32_t)(t) << 28) +#define RV32_TYPE_MASK (0xf << 28) +#define RV32_DMODE BIT(27) +#define RV64_TYPE(t) ((uint64_t)(t) << 60) +#define RV64_TYPE_MASK (0xfULL << 60) +#define RV64_DMODE BIT_ULL(59) + +/* mcontrol field masks */ + +#define TYPE2_LOAD BIT(0) +#define TYPE2_STORE BIT(1) +#define TYPE2_EXEC BIT(2) +#define TYPE2_U BIT(3) +#define TYPE2_S BIT(4) +#define TYPE2_M BIT(6) +#define TYPE2_MATCH (0xf << 7) +#define TYPE2_CHAIN BIT(11) +#define TYPE2_ACTION (0xf << 12) +#define TYPE2_SIZELO (0x3 << 16) +#define TYPE2_TIMING BIT(18) +#define TYPE2_SELECT BIT(19) +#define TYPE2_HIT BIT(20) +#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ + +/* access size */ +enum { + SIZE_ANY = 0, + SIZE_1B, + SIZE_2B, + SIZE_4B, + SIZE_6B, + SIZE_8B, + SIZE_10B, + SIZE_12B, + SIZE_14B, + SIZE_16B, + SIZE_NUM = 16 +}; + +bool tdata_available(CPURISCVState *env, int tdata_index); + +target_ulong tselect_csr_read(CPURISCVState *env); +void tselect_csr_write(CPURISCVState *env, target_ulong val); + +target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); +void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); + +#endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/debug.c b/target/riscv/debug.c new file mode 100644 index 0000000000..c8cec39217 --- /dev/null +++ b/target/riscv/debug.c @@ -0,0 +1,339 @@ +/* + * QEMU RISC-V Native Debug Support + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This provides the native debug support via the Trigger Module, as defined + * in the RISC-V Debug Specification: + * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "trace.h" +#include "exec/exec-all.h" + +/* + * The following M-mode trigger CSRs are implemented: + * + * - tselect + * - tdata1 + * - tdata2 + * - tdata3 + * + * We don't support writable 'type' field in the tdata1 register, so there is + * no need to implement the "tinfo" CSR. + * + * The following triggers are implemented: + * + * Index | Type | tdata mapping | Description + * ------+------+------------------------+------------ + * 0 | 2 | tdata1, tdata2 | Address / Data Match + * 1 | 2 | tdata1, tdata2 | Address / Data Match + */ + +/* tdata availability of a trigger */ +typedef bool tdata_avail[TDATA_NUM]; + +static tdata_avail tdata_mapping[TRIGGER_NUM] = { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = { true, true, false }, +}; + +/* only breakpoint size 1/2/4/8 supported */ +static int access_size[SIZE_NUM] = { + [SIZE_ANY] = 0, + [SIZE_1B] = 1, + [SIZE_2B] = 2, + [SIZE_4B] = 4, + [SIZE_6B] = -1, + [SIZE_8B] = 8, + [6 ... 15] = -1, +}; + +static inline target_ulong trigger_type(CPURISCVState *env, + trigger_type_t type) +{ + target_ulong tdata1; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + tdata1 = RV32_TYPE(type); + break; + case MXL_RV64: + tdata1 = RV64_TYPE(type); + break; + default: + g_assert_not_reached(); + } + + return tdata1; +} + +bool tdata_available(CPURISCVState *env, int tdata_index) +{ + if (unlikely(tdata_index >= TDATA_NUM)) { + return false; + } + + if (unlikely(env->trigger_cur >= TRIGGER_NUM)) { + return false; + } + + return tdata_mapping[env->trigger_cur][tdata_index]; +} + +target_ulong tselect_csr_read(CPURISCVState *env) +{ + return env->trigger_cur; +} + +void tselect_csr_write(CPURISCVState *env, target_ulong val) +{ + /* all target_ulong bits of tselect are implemented */ + env->trigger_cur = val; +} + +static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, + trigger_type_t t) +{ + uint32_t type, dmode; + target_ulong tdata1; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + type = extract32(val, 28, 4); + dmode = extract32(val, 27, 1); + tdata1 = RV32_TYPE(t); + break; + case MXL_RV64: + type = extract64(val, 60, 4); + dmode = extract64(val, 59, 1); + tdata1 = RV64_TYPE(t); + break; + default: + g_assert_not_reached(); + } + + if (type != t) { + qemu_log_mask(LOG_GUEST_ERROR, + "ignoring type write to tdata1 register\n"); + } + if (dmode != 0) { + qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n"); + } + + return tdata1; +} + +static inline void warn_always_zero_bit(target_ulong val, target_ulong mask, + const char *msg) +{ + if (val & mask) { + qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg); + } +} + +static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl) +{ + uint32_t size, sizelo, sizehi = 0; + + if (riscv_cpu_mxl(env) == MXL_RV64) { + sizehi = extract32(ctrl, 21, 2); + } + sizelo = extract32(ctrl, 16, 2); + size = (sizehi << 2) | sizelo; + + return size; +} + +static inline bool type2_breakpoint_enabled(target_ulong ctrl) +{ + bool mode = !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M)); + bool rwx = !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); + + return mode && rwx; +} + +static target_ulong type2_mcontrol_validate(CPURISCVState *env, + target_ulong ctrl) +{ + target_ulong val; + uint32_t size; + + /* validate the generic part first */ + val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); + + /* validate unimplemented (always zero) bits */ + warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); + warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); + warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); + warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); + warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); + warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); + + /* validate size encoding */ + size = type2_breakpoint_size(env, ctrl); + if (access_size[size] == -1) { + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n", + size); + } else { + val |= (ctrl & TYPE2_SIZELO); + if (riscv_cpu_mxl(env) == MXL_RV64) { + val |= (ctrl & TYPE2_SIZEHI); + } + } + + /* keep the mode and attribute bits */ + val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M | + TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); + + return val; +} + +static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) +{ + target_ulong ctrl = env->type2_trig[index].mcontrol; + target_ulong addr = env->type2_trig[index].maddress; + bool enabled = type2_breakpoint_enabled(ctrl); + CPUState *cs = env_cpu(env); + int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; + uint32_t size; + + if (!enabled) { + return; + } + + if (ctrl & TYPE2_EXEC) { + cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp); + } + + if (ctrl & TYPE2_LOAD) { + flags |= BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |= BP_MEM_WRITE; + } + + if (flags & BP_MEM_ACCESS) { + size = type2_breakpoint_size(env, ctrl); + if (size != 0) { + cpu_watchpoint_insert(cs, addr, size, flags, + &env->type2_trig[index].wp); + } else { + cpu_watchpoint_insert(cs, addr, 8, flags, + &env->type2_trig[index].wp); + } + } +} + +static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index) +{ + CPUState *cs = env_cpu(env); + + if (env->type2_trig[index].bp) { + cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp); + env->type2_trig[index].bp = NULL; + } + + if (env->type2_trig[index].wp) { + cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp); + env->type2_trig[index].wp = NULL; + } +} + +static target_ulong type2_reg_read(CPURISCVState *env, + target_ulong trigger_index, int tdata_index) +{ + uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0; + target_ulong tdata; + + switch (tdata_index) { + case TDATA1: + tdata = env->type2_trig[index].mcontrol; + break; + case TDATA2: + tdata = env->type2_trig[index].maddress; + break; + default: + g_assert_not_reached(); + } + + return tdata; +} + +static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index, + int tdata_index, target_ulong val) +{ + uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0; + target_ulong new_val; + + switch (tdata_index) { + case TDATA1: + new_val = type2_mcontrol_validate(env, val); + if (new_val != env->type2_trig[index].mcontrol) { + env->type2_trig[index].mcontrol = new_val; + type2_breakpoint_remove(env, index); + type2_breakpoint_insert(env, index); + } + break; + case TDATA2: + if (val != env->type2_trig[index].maddress) { + env->type2_trig[index].maddress = val; + type2_breakpoint_remove(env, index); + type2_breakpoint_insert(env, index); + } + break; + default: + g_assert_not_reached(); + } + + return; +} + +typedef target_ulong (*tdata_read_func)(CPURISCVState *env, + target_ulong trigger_index, + int tdata_index); + +static tdata_read_func trigger_read_funcs[TRIGGER_NUM] = { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_read, +}; + +typedef void (*tdata_write_func)(CPURISCVState *env, + target_ulong trigger_index, + int tdata_index, + target_ulong val); + +static tdata_write_func trigger_write_funcs[TRIGGER_NUM] = { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_write, +}; + +target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) +{ + tdata_read_func read_func = trigger_read_funcs[env->trigger_cur]; + + return read_func(env, env->trigger_cur, tdata_index); +} + +void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) +{ + tdata_write_func write_func = trigger_write_funcs[env->trigger_cur]; + + return write_func(env, env->trigger_cur, tdata_index, val); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 91f0ac32ff..2c20f3dd8e 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,6 +27,7 @@ riscv_softmmu_ss = ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'debug.c', 'monitor.c', 'machine.c' )) From patchwork Tue Mar 15 06:55:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1605464 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=BzpyaUay; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KHl9d3gSNz9sFy for ; Tue, 15 Mar 2022 18:17:57 +1100 (AEDT) Received: from localhost ([::1]:55634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU1RL-0007PY-GL for incoming@patchwork.ozlabs.org; Tue, 15 Mar 2022 03:17:55 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU15x-0007zK-0D; Tue, 15 Mar 2022 02:55:49 -0400 Received: from [2607:f8b0:4864:20::431] (port=43950 helo=mail-pf1-x431.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nU15v-0001td-Ld; Tue, 15 Mar 2022 02:55:48 -0400 Received: by mail-pf1-x431.google.com with SMTP id t2so15443682pfj.10; Mon, 14 Mar 2022 23:55:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OFB1A8Xyg8o44t2nNQnUN5pM95x45LdOb1NLqMmGO4w=; b=BzpyaUayewRMba4ml4+9c+UYP5ABlEHTf9yLmHmbXoqJgtE2MiTAkUWFS3HkEJCpMp p5UaJtD09efyf3EKJDryQyBoaurK9+KazhmYgyMdQox541LsJYbiakqlPq3UriD5XIf7 rWdqPX1Wai0XnlYKmaDb0fSmA/5SHjpdJPgs0D4/vrsubPnVApn3DmCWM2rqQ2NjG5EG NiqSI0qXRlkLxTXNkZCqgtP6eFaHslWYjeiW+8sv9f3zrjDAY0gDESlKNhJs0NcHrlbb 6CBmyXjF/Q0ptt6opUi9z+0kcH0e0g6pVRG2sh1DDo+mtwkLJjxxbKhQbd9bMDbPszMW 7++Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OFB1A8Xyg8o44t2nNQnUN5pM95x45LdOb1NLqMmGO4w=; b=c3SgEPRZzvFKk3ByOiRaOezmx2qbMQpIxArATTmtfszh4HaD6qThpGFtYDoMNO6NYg Cx6vVEqzT7pJSqpQiM3YNhp/PNsnb1bYSrxgoaVJ/h2wIGFczzQRanvKVUy2bpBAdPed aG2gpsAenBQz7qADwbfnqicyBsjI6xARk1BodI65YJN5z5GorKe82vZxcjXoVI0MwljN Sst1fpyPLuGhlGrornag7QT8eRu30FZSnjJEoanTK4aehXyK7FLBQCP9SJ4ok0pTOG2N xkDkS/MN1DvgOzV/gTZcithk4PRPhrhEM9LIVyIerycxhOK5xk5/CZRnKykRwrgeh33s d9pA== X-Gm-Message-State: AOAM530UVdCxMX6bqJwff7VvQT4E8bUqG7HwX9fNsRxKomzgIuP1QWSU KSrEPzYlDToBmmf80bZC1ywD9cDyZM8FgQ== X-Google-Smtp-Source: ABdhPJzpzp4TDd3TqJePLOEr4JwxzJLPZNKqRD6qSvzrByN25SDmANVWoy42U+DgGCjNqCQOVJh9hA== X-Received: by 2002:a65:41cc:0:b0:380:6f53:a550 with SMTP id b12-20020a6541cc000000b003806f53a550mr22836255pgq.471.1647327346125; Mon, 14 Mar 2022 23:55:46 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:55:45 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 2/7] target/riscv: machine: Add debug state description Date: Tue, 15 Mar 2022 14:55:24 +0800 Message-Id: <20220315065529.62198-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add a subsection to machine.c to migrate debug CSR state. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - new patch: add debug state description target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 5178b3fec9..4921dad09d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = { VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool debug_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_DEBUG); +} +static const VMStateDescription vmstate_debug_type2 = { + .name = "cpu/debug/type2", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(mcontrol, type2_trigger_t), + VMSTATE_UINTTL(maddress, type2_trigger_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_debug = { + .name = "cpu/debug", + .version_id = 1, + .minimum_version_id = 1, + .needed = debug_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), + VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM, + 0, vmstate_debug_type2, type2_trigger_t), VMSTATE_END_OF_LIST() } }; @@ -292,6 +323,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_debug, NULL } }; From patchwork Tue Mar 15 06:55:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1605465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=G+ld16Es; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KHlCr1hnFz9sFy for ; Tue, 15 Mar 2022 18:19:52 +1100 (AEDT) Received: from localhost ([::1]:33004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU1TC-0002s1-AW for incoming@patchwork.ozlabs.org; Tue, 15 Mar 2022 03:19:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU160-0008Ah-2i; Tue, 15 Mar 2022 02:55:52 -0400 Received: from [2607:f8b0:4864:20::42f] (port=42655 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nU15y-00024A-I8; Tue, 15 Mar 2022 02:55:51 -0400 Received: by mail-pf1-x42f.google.com with SMTP id g19so18130316pfc.9; Mon, 14 Mar 2022 23:55:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hHF+OMSx2VEEaQsfl4k82w4J9iz7dP0pqn45eGwLfg0=; b=G+ld16EsM+VEBoBG3cjM+e8o7EcECiIFf46HKeqIArRnz88NkVqC37kHCNCUDxaWIw lr8sJ2Kh+3pckO2tl2XBkePfCBQQCctNOHtWfnzjViJQDoSp46535RSxxVpt0EspQw1w 5uhGnn2l1jWo9yvzCnePfmYNMup6KfoMYXxcBNMSHLkoii2VIX0+XPJDxucblxinduq5 EGuq1mjNZXLuIikxdYxyV2+im0cnw3cuCRPeLA7jD4TSp0yngSHo8uPYXPtrMyRPTV8N XPwpOe1DJerThDGyclGbX635GnVUvLm2E+aJEX0Xjf7qPk4Ww5XtkWvIrZ/K2kSn6YVL NJ1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hHF+OMSx2VEEaQsfl4k82w4J9iz7dP0pqn45eGwLfg0=; b=NDaJq4cycQ5LaYQgusvrXke2FqxlSkwPpxISSbDli7lagQtea7fRrD7FJ3vxrdg57v L195ChQR8aQMPM4OlpoJ3KS3S1cIo6D2eBNtQrPKrkmfjbJHTiOlWNc568neu70kbEmF 7HdQTmrj8ZodxIxd1z1t1ZdgM5Ym+mBr40BeczL5Dw9j5PFZskilIzqlVR0OcSlXW9mg rDC2OxXAT+xJOM7hqA65+yOQoo4EGiRgoefal6HYeIT7Y7gPoxrjKY7DFmiJ1duVZnzn pjf7qqIBdj2aHNgglM6Fn1bptcF6P7lHhSCtBG4ydoT39cvglSj6UwcDddWrUMWfcJMD Obeg== X-Gm-Message-State: AOAM531LsWrQ/v7wUwdDUWS44dWPt/65RUytozEHfIFkux3d8/Guy5HK yW5kLCumJG+82qsXz5JmHaQ= X-Google-Smtp-Source: ABdhPJzDEBfqdODovr9UfzmqUnWkahuqkJl6okT+5UGH+qiWoss6RxyT1iqvh3dLbyl1wCq68hp8vw== X-Received: by 2002:a63:4f43:0:b0:378:8ec6:7936 with SMTP id p3-20020a634f43000000b003788ec67936mr22567661pgl.329.1647327349050; Mon, 14 Mar 2022 23:55:49 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:55:48 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps Date: Tue, 15 Mar 2022 14:55:25 +0800 Message-Id: <20220315065529.62198-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - use 0 instead of GETPC() target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index fbc5f946e2..fb21706e1c 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); +void riscv_cpu_debug_excp_handler(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..6a4c94da2a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -865,6 +865,9 @@ static const struct TCGCPUOps riscv_tcg_ops = { .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, + .debug_excp_handler = riscv_cpu_debug_excp_handler, + .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index c8cec39217..1a9392645e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) return write_func(env, env->trigger_cur, tdata_index, val); } + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl = env->type2_trig[i].mcontrol; + pc = env->type2_trig[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + target_ulong ctrl; + target_ulong addr; + int flags; + int i; + + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl = env->type2_trig[i].mcontrol; + addr = env->type2_trig[i].maddress; + flags = 0; + + if (ctrl & TYPE2_LOAD) { + flags |= BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |= BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr == addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + + return false; +} From patchwork Tue Mar 15 06:55:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1605451 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:55:52 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug Date: Tue, 15 Mar 2022 14:55:26 +0800 Message-Id: <20220315065529.62198-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add a config option to enable support for native M-mode debug. This is disabled by default and can be enabled with 'debug=true'. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - change the config option to 'disabled' by default target/riscv/cpu.h | 4 +++- target/riscv/cpu.c | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad35129239..d3e884452b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,7 +79,8 @@ enum { RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA, - RISCV_FEATURE_AIA + RISCV_FEATURE_AIA, + RISCV_FEATURE_DEBUG }; #define PRIV_VERSION_1_10_0 0x00011000 @@ -388,6 +389,7 @@ struct RISCVCPUConfig { bool pmp; bool epmp; bool aia; + bool debug; uint64_t resetvec; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a4c94da2a..eb2be5fa05 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -541,6 +541,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_AIA); } + if (cpu->cfg.debug) { + riscv_set_feature(env, RISCV_FEATURE_DEBUG); + } + set_resetvec(env, cpu->cfg.resetvec); /* Validate that MISA_MXL is set properly. */ @@ -780,6 +784,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), From patchwork Tue Mar 15 06:55:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1605456 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=nLDeeek+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KHkzb1Pngz9sFq for ; Tue, 15 Mar 2022 18:09:15 +1100 (AEDT) Received: from localhost ([::1]:38264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU1Iv-0003xP-9S for incoming@patchwork.ozlabs.org; Tue, 15 Mar 2022 03:09:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU167-0008VW-8j; Tue, 15 Mar 2022 02:56:00 -0400 Received: from [2607:f8b0:4864:20::430] (port=37399 helo=mail-pf1-x430.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nU165-00024e-IP; Tue, 15 Mar 2022 02:55:59 -0400 Received: by mail-pf1-x430.google.com with SMTP id t5so18136602pfg.4; Mon, 14 Mar 2022 23:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jHSkv0qE2OlmJxavDPt8a/C4lvFDwFk2dnqGbzwfFDQ=; b=nLDeeek+uoVKS1ZzOUs05TtQ+M3va8Pog1ydQAMMJzXrP71hfJWdSDVQxnCLOYk4aN pUtYCMnvuR0H/akHegovUAlEN8bwmLM7VUYp3dW7dyfdFqVqvF9XoYMeveOl2nlHeSjI XOmmGxtVWYdViZOhEgVVOOZVE56kZYPiCtbG4k+zkOBoMlnMXQvvN6x2EpKEHOii9fqh X+8LrIsBp8UE/7UhSZWjK0LFruUXk/oooJex1F6jhDTNoCCjg9zhNrE3Fi697Qp+xctl GfZM5Fxw8Z0pvHnCDVktecGhMJSTATqncrgmGbUpqvKZRFAJanvyE39RIS2rgB4lJCjR FQ7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jHSkv0qE2OlmJxavDPt8a/C4lvFDwFk2dnqGbzwfFDQ=; b=NgWbRCTmIJKDN7ZHKIj5tKKCdItZBtoWHrq5HpY9/G5TCjMd5q4CqsO3CZjZ7rPVFY s6iwU+3CWkSfiVuIX1ky/owQtkUcr2zre8lLj13BKOzzW00j79tTA0boLINJHPv5BBWo itIIykK6dfaCDGXoikkKVsvuKsV/ZbK374IM++sFBV67LzgDDl0NEt6GrPq+E06gJjBY qbRhgazdPBUnUN+IMuKcv2fLNk5wjPT/e4xAouTFwnZ+BFidIwE5yRf3kNMwDB1uVXSc uPQbAEPOZroFLI6kbG07DNAjWGGNTzHTAEp6/mXDeY4rk7ov04HcgQZWTN6H4ENREK7K rscA== X-Gm-Message-State: AOAM530PP/LmXA8zIzJ/CecX1GW+wMHzHHmzY/6xc9KvSnDTNwXiJDEc BZwuGZ0BbVdP9SncZi/A/Kc= X-Google-Smtp-Source: ABdhPJy5qjVehqd8ooN+FrhcWYtLs+6JsVBIejZpPhOlPEhDpe5LfJwNsj8kgCvf92bm1thj/qzvhA== X-Received: by 2002:a62:63c1:0:b0:4f6:f215:93cb with SMTP id x184-20020a6263c1000000b004f6f21593cbmr27140666pfb.81.1647327355854; Mon, 14 Mar 2022 23:55:55 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:55:55 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write Date: Tue, 15 Mar 2022 14:55:27 +0800 Message-Id: <20220315065529.62198-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v4: - move riscv_trigger_init() call to riscv_cpu_reset() Changes in v3: - add riscv_trigger_init(), moved from patch #1 to this patch target/riscv/debug.h | 2 ++ target/riscv/cpu.c | 4 ++++ target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/riscv/debug.c | 27 +++++++++++++++++++++ 4 files changed, 90 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index fb21706e1c..27b9cac6b4 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); +void riscv_trigger_init(CPURISCVState *env); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb2be5fa05..ba9cc3bcd6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -461,6 +461,10 @@ static void riscv_cpu_reset(DeviceState *dev) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + riscv_trigger_init(env); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0606cd0ea8..3b9008709d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException debug(CPURISCVState *env, int csrno) +{ + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif /* User Floating-Point CSRs */ @@ -2576,6 +2585,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_tselect(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = tselect_csr_read(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tselect(CPURISCVState *env, int csrno, + target_ulong val) +{ + tselect_csr_write(env, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_tdata(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* return 0 in tdata1 to end the trigger enumeration */ + if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { + *val = 0; + return RISCV_EXCP_NONE; + } + + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val = tdata_csr_read(env, csrno - CSR_TDATA1); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tdata(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + tdata_csr_write(env, csrno - CSR_TDATA1, val); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -3265,6 +3316,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + /* Debug CSRs */ + [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, + [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, + [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, + [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, + /* User Pointer Masking */ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 1a9392645e..2f2a51c732 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) return false; } + +void riscv_trigger_init(CPURISCVState *env) +{ + target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH); + int i; + + /* type 2 triggers */ + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + /* + * type = TRIGGER_TYPE_AD_MATCH + * dmode = 0 (both debug and M-mode can write tdata) + * maskmax = 0 (unimplemented, always 0) + * sizehi = 0 (match against any size, RV64 only) + * hit = 0 (unimplemented, always 0) + * select = 0 (always 0, perform match on address) + * timing = 0 (always 0, trigger before instruction) + * sizelo = 0 (match against any size) + * action = 0 (always 0, raise a breakpoint exception) + * chain = 0 (unimplemented, always 0) + * match = 0 (always 0, when any compare value equals tdata2) + */ + env->type2_trig[i].mcontrol = type2; + env->type2_trig[i].maddress = 0; + env->type2_trig[i].bp = NULL; + env->type2_trig[i].wp = NULL; + } +} From patchwork Tue Mar 15 06:55:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1605449 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:55:58 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature Date: Tue, 15 Mar 2022 14:55:28 +0800 Message-Id: <20220315065529.62198-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Turn on native debug feature by default for all CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - enable debug feature by default for all CPUs target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ba9cc3bcd6..08266b163d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -788,7 +788,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), From patchwork Tue Mar 15 06:55:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1605460 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=c7Gal8DI; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KHl330g3Jz9sFy for ; Tue, 15 Mar 2022 18:12:15 +1100 (AEDT) Received: from localhost ([::1]:45544 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU1Lo-0000VN-Vw for incoming@patchwork.ozlabs.org; Tue, 15 Mar 2022 03:12:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU16H-0000HY-3m; Tue, 15 Mar 2022 02:56:09 -0400 Received: from [2607:f8b0:4864:20::431] (port=41795 helo=mail-pf1-x431.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nU16C-00025H-0J; Tue, 15 Mar 2022 02:56:08 -0400 Received: by mail-pf1-x431.google.com with SMTP id p8so18125548pfh.8; Mon, 14 Mar 2022 23:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k03hqsrN3r2DAcpcEZo3Qmaha1XCoOaXcqqhAGM9cU0=; b=c7Gal8DI557IDAn7fC7jLhOGB31o7BknPQefKUSIWASKtYZ3wiud/sVngQCG7xv75e psNNvl2F+qmv445eR0iyn353P7Rj53O/mnuh2qRIwGYJBawhrA5XOODroeS9FcXSy95q 9dn63upwBqGtVlyRj2aS3ct/MaNiGgTnmZlxdf+QOzsqEXicBVnUEvSQB/R4FMiipHL1 JV1YGkhjy991deROESbU5jkjaciBcfGccvcftfgsWThAIyhjlTzVx+bLg4XDcH5eSgUz 6aT6q+tisk0GRr9pnPGv56Pv0ck2PxTzNxX29Z5St7nX6wJ5Ak81YwPQ0kC3vepkCz6b 4SeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k03hqsrN3r2DAcpcEZo3Qmaha1XCoOaXcqqhAGM9cU0=; b=iXXOu5nvIdrRpbpE6nURtDrOMivH4DOD+aH0jEtlEGPSTTFu26ni3k2ScyBAsRHwY5 0grgyCsTNB8EP8w8tmFrxYgGzZBwnN2kUEBIBarlGJX3kBm9pQVQs6IwLXV2FKc9q7NU C5KFyiEnL1lpFHw65uLm6dyZI1JVWixvoay0SOOrZAeYXkfsKA7P+jIUItoDZxjl503c DShgSi3PGTy4UhfMsXzj5gz1Fh7P4z5AhL74aOLXQfVmn10fAzTRSJ+TqdIzRT2esCLu /Fsz4RyQQnFt78MKv/bxy9ro821h1xq+xDzedm4ydoMhdnXDcOaboqcrWiGFy4E0mwM1 VWVw== X-Gm-Message-State: AOAM531zOyHcopOBzVaFoIkBcUCer59RAkOJzD+1/xrdsCz3YBweosGS 20XC+RHYJGjeJ9Yp2E9jjH6lM6xTI6DCjw== X-Google-Smtp-Source: ABdhPJz4SRjh3K1lHVQaEubYk88LkkfmEkyeLX4rLdr9C6RBS2CnKoGatPxYiOUz3QctJnO959ISxg== X-Received: by 2002:a63:2d05:0:b0:34b:3f1d:2fa8 with SMTP id t5-20020a632d05000000b0034b3f1d2fa8mr23200013pgt.447.1647327361892; Mon, 14 Mar 2022 23:56:01 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id g12-20020a056a001a0c00b004e1307b249csm22970500pfv.69.2022.03.14.23.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 23:56:01 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Date: Tue, 15 Mar 2022 14:55:29 +0800 Message-Id: <20220315065529.62198-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com> References: <20220315065529.62198-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/core/tcg-cpu-ops.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e13898553a..f98671ff32 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -90,6 +90,7 @@ struct TCGCPUOps { /** * @debug_check_watchpoint: return true if the architectural * watchpoint whose address has matched should really fire, used by ARM + * and RISC-V */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);