| Message ID | 1566191521-7820-21-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand |
On Sun, Aug 18, 2019 at 10:24 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Now that we have added a PRCI node, update existing UART and ethernet > nodes to reference PRCI as their clock sources, to keep in sync with > the Linux kernel device tree. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > hw/riscv/sifive_u.c | 7 ++++--- > include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ > 2 files changed, 14 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index bd5551c..8818fd6 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -80,7 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > int cpu; > uint32_t *cells; > char *nodename; > - char ethclk_names[] = "pclk\0hclk\0tx_clk"; > + char ethclk_names[] = "pclk\0hclk"; > uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; > uint32_t uartclk_phandle; > uint32_t hfclk_phandle, rtcclk_phandle; > @@ -265,7 +265,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); > qemu_fdt_setprop_cells(fdt, nodename, "clocks", > - ethclk_phandle, ethclk_phandle, ethclk_phandle); > + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); > qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, > sizeof(ethclk_names)); > qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); > @@ -295,7 +295,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cells(fdt, nodename, "reg", > 0x0, memmap[SIFIVE_U_UART0].base, > 0x0, memmap[SIFIVE_U_UART0].size); > - qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + prci_phandle, PRCI_CLK_TLCLK); > qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); > > diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h > index 66eacb5..cdf1d33 100644 > --- a/include/hw/riscv/sifive_u_prci.h > +++ b/include/hw/riscv/sifive_u_prci.h > @@ -87,4 +87,14 @@ typedef struct SiFiveUPRCIState { > > DeviceState *sifive_u_prci_create(hwaddr addr); > > +/* > + * Clock indexes for use by Device Tree data and the PRCI driver. > + * > + * These values are from sifive-fu540-prci.h in the Linux kernel. > + */ > +#define PRCI_CLK_COREPLL 0 > +#define PRCI_CLK_DDRPLL 1 > +#define PRCI_CLK_GEMGXLPLL 2 > +#define PRCI_CLK_TLCLK 3 > + > #endif /* HW_SIFIVE_U_PRCI_H */ > -- > 2.7.4 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bd5551c..8818fd6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -80,7 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] = "pclk\0hclk\0tx_clk"; + char ethclk_names[] = "pclk\0hclk"; uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; uint32_t uartclk_phandle; uint32_t hfclk_phandle, rtcclk_phandle; @@ -265,7 +265,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", - ethclk_phandle, ethclk_phandle, ethclk_phandle); + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); @@ -295,7 +295,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h index 66eacb5..cdf1d33 100644 --- a/include/hw/riscv/sifive_u_prci.h +++ b/include/hw/riscv/sifive_u_prci.h @@ -87,4 +87,14 @@ typedef struct SiFiveUPRCIState { DeviceState *sifive_u_prci_create(hwaddr addr); +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + #endif /* HW_SIFIVE_U_PRCI_H */
Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 7 ++++--- include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ 2 files changed, 14 insertions(+), 3 deletions(-)