| Message ID | 20220704085552.3499243-2-abel@x-silicon.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/2] package/llvm: Support for RISC-V on the LLVM package | expand |
Hello Adel, Le 04/07/2022 à 10:55, Abel Bernabeu a écrit : > This new setting will allow to test new toolchains already available > that support the vector extension (more patches coming soon). We received a similar patch [1] from another contributor. Actually this is the same content with the same missing dependency on gcc-12. See also a comment [2]: "Yes, V definitely needs an option, as there will clearly be Linux-capable RISC-V cores that do not implement the V extension. The option for the V extension will have to select BR2_ARCH_NEEDS_GCC_AT_LEAST_12." [1] http://lists.busybox.net/pipermail/buildroot/2022-June/645381.html [2] http://lists.busybox.net/pipermail/buildroot/2022-July/646724.html See how to review patches: https://nightly.buildroot.org/manual.html#_reviewing_and_testing_patches I have marked this patch as "Changes Requested". Best regards, Romain > > Signed-off-by: Abel Bernabeu <abel@x-silicon.com> > --- > arch/Config.in.riscv | 7 +++++++ > arch/arch.mk.riscv | 4 ++++ > 2 files changed, 11 insertions(+) > > diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv > index 288ed833eb..e4dc936cf8 100644 > --- a/arch/Config.in.riscv > +++ b/arch/Config.in.riscv > @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD > config BR2_RISCV_ISA_RVC > bool > > +config BR2_RISCV_ISA_RVV > + bool > + > choice > prompt "Target Architecture Variant" > default BR2_riscv_g > @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD > config BR2_RISCV_ISA_CUSTOM_RVC > bool "Compressed Instructions (C)" > select BR2_RISCV_ISA_RVC > + > +config BR2_RISCV_ISA_CUSTOM_RVV > + bool "Vector Instructions (V)" > + select BR2_RISCV_ISA_RVV > endif > > choice > diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv > index f3bf2b3467..07a94aa6a4 100644 > --- a/arch/arch.mk.riscv > +++ b/arch/arch.mk.riscv > @@ -26,5 +26,9 @@ endif > ifeq ($(BR2_RISCV_ISA_RVC),y) > GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c > endif > +ifeq ($(BR2_RISCV_ISA_RVV),y) > +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v > +endif > + > > endif
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 288ed833eb..e4dc936cf8 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD config BR2_RISCV_ISA_RVC bool +config BR2_RISCV_ISA_RVV + bool + choice prompt "Target Architecture Variant" default BR2_riscv_g @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD config BR2_RISCV_ISA_CUSTOM_RVC bool "Compressed Instructions (C)" select BR2_RISCV_ISA_RVC + +config BR2_RISCV_ISA_CUSTOM_RVV + bool "Vector Instructions (V)" + select BR2_RISCV_ISA_RVV endif choice diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv index f3bf2b3467..07a94aa6a4 100644 --- a/arch/arch.mk.riscv +++ b/arch/arch.mk.riscv @@ -26,5 +26,9 @@ endif ifeq ($(BR2_RISCV_ISA_RVC),y) GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c endif +ifeq ($(BR2_RISCV_ISA_RVV),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v +endif + endif
This new setting will allow to test new toolchains already available that support the vector extension (more patches coming soon). Signed-off-by: Abel Bernabeu <abel@x-silicon.com> --- arch/Config.in.riscv | 7 +++++++ arch/arch.mk.riscv | 4 ++++ 2 files changed, 11 insertions(+)