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[95.23.5.14]) by smtp.gmail.com with ESMTPSA id f18-20020adff992000000b0021b9416fa13sm6624967wrr.90.2022.07.04.01.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 01:55:59 -0700 (PDT) From: Abel Bernabeu To: buildroot@buildroot.org Date: Mon, 4 Jul 2022 10:55:52 +0200 Message-Id: <20220704085552.3499243-2-abel@x-silicon.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220704085552.3499243-1-abel@x-silicon.com> References: <20220704085552.3499243-1-abel@x-silicon.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=x-silicon-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XEcwkc6CukaKyaQvKEoM2mjWb0wdqLDUqxUGanRWMZ8=; b=QiujlS33dv9ISRHM1xlKOnxnNKcSdC9l9NvCw1V01Kp6hpIbo/FmAqVs/e2NmQJRL0 przYfTuHdR2ww1RIHEZ117g9+f+/CMGD6f2rcJ9odwlutTpeodwTiT45aJ+jYYBAcWNi HVoIUoznkZyFC0iLpOITK6JLo4qvYK9HyqCWGRin9dn7hpoChYjM479CgOjoM9YEELQT uc2DbHRpsLdJ/B0gwLkh0ix4Z8vPLSjo40UTs/Y88GohU9d01rpmilg5ePuYzWTkDtQt Y58RxlleScmvkvFvLrCq1n3aegVveS88WLmZHiyanZ3DGLOSAzQvI/h32A/NRjifWn41 aMgg== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=x-silicon-com.20210112.gappssmtp.com header.i=@x-silicon-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=QiujlS33 Subject: [Buildroot] [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu. X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joseph Kogut , Romain Naour , Mark Corbin , Abel Bernabeu , Valentin Korenblit Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" This new setting will allow to test new toolchains already available that support the vector extension (more patches coming soon). Signed-off-by: Abel Bernabeu --- arch/Config.in.riscv | 7 +++++++ arch/arch.mk.riscv | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 288ed833eb..e4dc936cf8 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD config BR2_RISCV_ISA_RVC bool +config BR2_RISCV_ISA_RVV + bool + choice prompt "Target Architecture Variant" default BR2_riscv_g @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD config BR2_RISCV_ISA_CUSTOM_RVC bool "Compressed Instructions (C)" select BR2_RISCV_ISA_RVC + +config BR2_RISCV_ISA_CUSTOM_RVV + bool "Vector Instructions (V)" + select BR2_RISCV_ISA_RVV endif choice diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv index f3bf2b3467..07a94aa6a4 100644 --- a/arch/arch.mk.riscv +++ b/arch/arch.mk.riscv @@ -26,5 +26,9 @@ endif ifeq ($(BR2_RISCV_ISA_RVC),y) GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c endif +ifeq ($(BR2_RISCV_ISA_RVV),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v +endif + endif