| Message ID | 20220513021514.3363-1-dinesh.maniyam@intel.com |
|---|---|
| State | Deferred |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | arm: socfpga: mailbox: Add mailbox command for HPS execution notifcation | expand |
> -----Original Message----- > From: Maniyam, Dinesh <dinesh.maniyam@intel.com> > Sent: Friday, 13 May, 2022 10:15 AM > To: u-boot@lists.denx.de > Cc: Vasut, Marek <marex@denx.de>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Hea, Kok Kiang <kok.kiang.hea@intel.com>; > Gan, Yau Wai <yau.wai.gan@intel.com>; Kho, Sin Hui > <sin.hui.kho@intel.com>; Lokanathan, Raaj <raaj.lokanathan@intel.com>; > Maniyam, Dinesh <dinesh.maniyam@intel.com> > Subject: [PATCH] arm: socfpga: mailbox: Add mailbox command for HPS > execution notifcation > > From: Dinesh Maniyam <dinesh.maniyam@intel.com> > > Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device > Manager (SDM) on the stage of HPS code execution. In general, there are > three main code execution stages: First Stage Boot Loader (FSBL) which is U- > Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the > Operating System which is Linux. > > Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> > --- > arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ > arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h > b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h > index fbaf11597e..50fe6393f9 100644 > --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h > +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h > @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE { > #define MBOX_QSPI_CLOSE 51 > #define MBOX_QSPI_DIRECT 59 > #define MBOX_REBOOT_HPS 71 > +#define MBOX_HPS_STAGE_NOTIFY 93 > > /* Mailbox registers */ > #define MBOX_CIN 0 /* command valid offset */ > @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE { > #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) > #define RCF_PIN_STATUS_NSTATUS BIT(31) > > +/* Defines for HPS_STAGE_NOTIFY */ > +#define HPS_EXECUTION_STATE_FSBL 0 > +#define HPS_EXECUTION_STATE_SSBL 1 > +#define HPS_EXECUTION_STATE_OS 2 > + > int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 > urgent, > u32 *resp_buf_len, u32 *resp_buf); > int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, > @@ -182,6 +188,7 @@ int mbox_qspi_open(void); #endif > > int mbox_reset_cold(void); > +int mbox_hps_stage_notify(u32 execution_stage); > int mbox_get_fpga_config_status(u32 cmd); int > mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ > */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach- > socfpga/mailbox_s10.c > index 101af23855..99f78c7c32 100644 > --- a/arch/arm/mach-socfpga/mailbox_s10.c > +++ b/arch/arm/mach-socfpga/mailbox_s10.c > @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, > u8 is_indirect, u32 len, > urgent, resp_buf_len, resp_buf); } > > +int mbox_hps_stage_notify(u32 execution_stage) { > + return mbox_send_cmd(MBOX_ID_UBOOT, > MBOX_HPS_STAGE_NOTIFY, > + MBOX_CMD_DIRECT, 1, &execution_stage, 0, > 0, NULL); } > + Please fix the alignment issue above. Please extend the year of copyright. > int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { > return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); > -- > 2.26.2
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597e..50fe6393f9 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 /* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31) +/* Defines for HPS_STAGE_NOTIFY */ +#define HPS_EXECUTION_STATE_FSBL 0 +#define HPS_EXECUTION_STATE_SSBL 1 +#define HPS_EXECUTION_STATE_OS 2 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -182,6 +188,7 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 101af23855..99f78c7c32 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); } +int mbox_hps_stage_notify(u32 execution_stage) +{ + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);