From patchwork Fri May 13 02:15:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maniyam, Dinesh" X-Patchwork-Id: 1630474 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=cW9cuJED; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KztLX2qbxz9sG3 for ; Fri, 13 May 2022 12:45:56 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 75C6683E43; Fri, 13 May 2022 04:45:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cW9cuJED"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3BA7C839B9; Fri, 13 May 2022 04:15:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7E0EF83B20 for ; Fri, 13 May 2022 04:15:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dinesh.maniyam@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652408123; x=1683944123; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=rEij0j/0AHIRDx0mBbeQYZXuZNu54TxGvcmaI47g1wU=; b=cW9cuJEDA04JkucXTPphSDJXJQRSleOUu7MUdXbGvOX9GzQ+AgT6L/lz 7cdTaPUd4d/wfwmP258xey2SC+j/0BUFGL8yflNX03fsRv5eaDyImcTaG 4AqlMIwpabtjCSU+IqB+eYfda+2/WVcXPBGiVWGL3RjlCxLGJ+yBCmjZd k6w11pv/ayxs0D6aVBLH3LaTpGxTQaVG+B8X2NPrOYUcgagX5RKwlUBlO V6tqoiZ0WDcw4eGOw0evhnR7zzvT2jTNvjTAo2wLzSUmg6ozPK0cPY+Ij EToP3fIBAuinn+NRn0NDdhjzRjpjmrM9DQmsQlXz+zXvafCjCaKrgYkw+ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10345"; a="295449949" X-IronPort-AV: E=Sophos;i="5.91,221,1647327600"; d="scan'208";a="295449949" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 19:15:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,221,1647327600"; d="scan'208";a="637101263" Received: from pglc1230.png.intel.com ([10.221.139.25]) by fmsmga004.fm.intel.com with ESMTP; 12 May 2022 19:15:17 -0700 From: dinesh.maniyam@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Tien Fong Chee , Kok Kiang , Yau Wai , Sin Hui , Raaj , Dinesh Maniyam Subject: [PATCH] arm: socfpga: mailbox: Add mailbox command for HPS execution notifcation Date: Fri, 13 May 2022 10:15:14 +0800 Message-Id: <20220513021514.3363-1-dinesh.maniyam@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 13 May 2022 04:45:52 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Dinesh Maniyam Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System which is Linux. Signed-off-by: Dinesh Maniyam --- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ 2 files changed, 13 insertions(+) -- 2.26.2 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597e..50fe6393f9 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 /* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31) +/* Defines for HPS_STAGE_NOTIFY */ +#define HPS_EXECUTION_STATE_FSBL 0 +#define HPS_EXECUTION_STATE_SSBL 1 +#define HPS_EXECUTION_STATE_OS 2 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -182,6 +188,7 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 101af23855..99f78c7c32 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); } +int mbox_hps_stage_notify(u32 execution_stage) +{ + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);