| Message ID | 20200214160829.27994-1-alifer.wsdm@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Stefano Babic |
| Headers | show |
| Series | [1/3] clk: imx: imx8mn: add enet clk | expand |
Hi Alifer, > Add enet ref/timer/PHY_REF/root clk wich are required to make enet > work properly Why have you sent those patches twice? > > Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com> > --- > drivers/clk/imx/clk-imx8mn.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/clk/imx/clk-imx8mn.c > b/drivers/clk/imx/clk-imx8mn.c index eb43971ae6..103ba770ed 100644 > --- a/drivers/clk/imx/clk-imx8mn.c > +++ b/drivers/clk/imx/clk-imx8mn.c > @@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] = > {"clock-osc-24m", "sys_pll1_133m", "sys_p static const char > *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", > "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", > "video_pll1_out", "sys_pll3_out", }; +#ifndef CONFIG_SPL_BUILD > +static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", > "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", > + "sys_pll1_160m", > "audio_pll1_out", "video_pll1_out", "clk_ext4", }; + > +static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", > "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", > + "clk_ext3", > "clk_ext4", "video_pll1_out", }; + > +static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", > "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", > + "sys_pll2_500m", > "video_pll1_out", "audio_pll2_out", }; +#endif > + > static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", > "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", > "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; > @@ -363,6 +374,14 @@ static int imx8mn_clk_probe(struct udevice *dev) > clk_dm(IMX8MN_CLK_USDHC3_ROOT, > imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + > 0x45e0, 0)); > +/* clks not needed in SPL stage */ > +#ifndef CONFIG_SPL_BUILD > + clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref", > imx8mn_enet_ref_sels, base + 0xa980)); > + clk_dm(IMX8MN_CLK_ENET_TIMER, > imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + > 0xaa00)); > + clk_dm(IMX8MN_CLK_ENET_PHY_REF, > imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80)); > + clk_dm(IMX8MN_CLK_ENET1_ROOT, > imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); > +#endif + > #ifdef CONFIG_SPL_BUILD > struct clk *clkp, *clkp1; > Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Hello Lukasz, > Why have you sent those patches twice? > I'm sorry for that, the first time I sent this patch I forgot to send to u-boot lists too, so I sent it again. Regards, Alifer
Hi Alifer, > Hello Lukasz, > > > Why have you sent those patches twice? > > > > I'm sorry for that, I was just curious if you made a v2 :-) > the first time I sent this patch I forgot to send > to u-boot lists too, so I sent it again. > > Regards, > Alifer Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index eb43971ae6..103ba770ed 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_p static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; +#ifndef CONFIG_SPL_BUILD +static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", + "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; + +static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4", "video_pll1_out", }; + +static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", + "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; +#endif + static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; @@ -363,6 +374,14 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); +/* clks not needed in SPL stage */ +#ifndef CONFIG_SPL_BUILD + clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980)); + clk_dm(IMX8MN_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00)); + clk_dm(IMX8MN_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80)); + clk_dm(IMX8MN_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); +#endif + #ifdef CONFIG_SPL_BUILD struct clk *clkp, *clkp1;
Add enet ref/timer/PHY_REF/root clk wich are required to make enet work properly Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com> --- drivers/clk/imx/clk-imx8mn.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)