diff mbox series

[18/19] mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash

Message ID 9d170c76facf4278a3b0b0059455e4bf0735e497.1710098033.git.tejas.arvind.bhumkar@amd.com
State New
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series Add support for DDR PHY mode | expand

Commit Message

Bhumkar, Tejas Arvind March 11, 2024, 5:22 p.m. UTC 
Enable the utilization of mt35xu512aba_fixups for GIGADEVICE
octal flash to operate in DDR mode.

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
---
 drivers/mtd/spi/spi-nor-core.c | 9 ++++++++-
 drivers/mtd/spi/spi-nor-ids.c  | 2 +-
 2 files changed, 9 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 27579cbf15..6b396ce681 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3977,7 +3977,7 @@  static struct spi_nor_fixups s28hx_t_fixups = {
 };
 #endif /* CONFIG_SPI_FLASH_S28HX_T */
 
-#if defined(CONFIG_SPI_FLASH_MT35XU) || defined(CONFIG_SPI_FLASH_ISSI)
+#if defined(CONFIG_SPI_FLASH_MT35XU) || defined(CONFIG_SPI_FLASH_ISSI) || defined(CONFIG_SPI_FLASH_GIGADEVICE)
 static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
 {
 	struct spi_mem_op op;
@@ -4356,6 +4356,13 @@  void spi_nor_set_fixups(struct spi_nor *nor)
 	}
 #endif
 
+#if defined(CONFIG_SPI_FLASH_GIGADEVICE)
+	if (!strcmp(nor->info->name, "gd25lx256e")) {
+		nor->fixups = &mt35xu512aba_fixups;
+		return;
+	}
+#endif
+
 #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
 	nor->fixups = &macronix_octal_fixups;
 #endif /* SPI_FLASH_MACRONIX */
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index c5c46c1a0c..34fba49592 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -192,7 +192,7 @@  const struct flash_info spi_nor_ids[] = {
 	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
 	{
 		INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
-		     SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
+		     SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
 	},
 	/* adding these 1.8V OSPI flash parts */
 	{INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024,	SECT_4K |