Message ID | 20190904103151.20121-15-lokeshvutla@ti.com |
---|---|
State | Accepted |
Commit | 293e39780d5f03c3ce8a2b032b607a9cf161d9fc |
Delegated to: | Tom Rini |
Headers | show |
Series | remoteproc: Add support for R5F and DSP processors | expand |
On Wed, Sep 04, 2019 at 04:01:39PM +0530, Lokesh Vutla wrote: > The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) > in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP > Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional > 288 KB of L2 configurable SRAM/Cache. These subsystems do not have > an MMU but contain a Region Address Translator (RAT) sub-module for > translating 32-bit processor addresses into larger bus addresses. > The inter-processor communication between the main A72 cores and > these processors is achieved through shared memory and Mailboxes. > Add the DT nodes for these DSP processor sub-systems in the common > k3-j721e-main.dtsi file. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index 21afdc8ce0..a548277718 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -20,6 +20,8 @@ remoteproc3 = &main_r5fss0_core1; remoteproc4 = &main_r5fss1_core0; remoteproc5 = &main_r5fss1_core1; + remoteproc6 = &c66_0; + remoteproc7 = &c66_1; }; }; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 59ca4e5686..c3aa0cdcf1 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -304,4 +304,28 @@ loczrama = <1>; }; }; + + c66_0: dsp@4d80800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x80800000 0x00 0x00048000>, + <0x4d 0x80e00000 0x00 0x00008000>, + <0x4d 0x80f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <142>; + ti,sci-proc-ids = <0x03 0xFF>; + resets = <&k3_reset 142 1>; + }; + + c66_1: dsp@4d81800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x81800000 0x00 0x00048000>, + <0x4d 0x81e00000 0x00 0x00008000>, + <0x4d 0x81f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <143>; + ti,sci-proc-ids = <0x04 0xFF>; + resets = <&k3_reset 143 1>; + }; };