| Message ID | 20190904103151.20121-13-lokeshvutla@ti.com |
|---|---|
| State | Accepted |
| Commit | b9f035e9c8c87510a01dd4228ea19b4e9a5a8734 |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | remoteproc: Add support for R5F and DSP processors | expand |
On Wed, Sep 04, 2019 at 04:01:37PM +0530, Lokesh Vutla wrote: > The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) > subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within > the MCU domain, and the remaining two clusters are present in the > MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be > configured at boot time to be either run in a LockStep mode or in > an Asymmetric Multi Processing (AMP) fashion in Split-mode. These > subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal > memories for each core split between two banks - ATCM and BTCM > (further interleaved into two banks). There are some IP integration > differences from standard Arm R5 clusters such as the absence of > an ACP port, presence of an additional TI-specific Region Address > Translater (RAT) module for translating 32-bit CPU addresses into > larger system bus addresses etc. > > Add the DT node for the MCU domain R5F cluster/subsystem, the two > R5 cores are added as child nodes to the main cluster/subsystem node. > The cluster is configured to run in LockStep mode by default, with the > ATCMs enabled to allow the R5 cores to execute code from DDR with > boot-strapping code from ATCM. The inter-processor communication > between the main A72 cores and these processors is achieved through > shared memory and Mailboxes. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index b5b8c3c5cc..070d21cd05 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -12,6 +12,11 @@ stdout-path = "serial2:115200n8"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + + aliases { + remoteproc0 = &mcu_r5fss0_core0; + remoteproc1 = &mcu_r5fss0_core1; + }; }; &wkup_uart0 { diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 1175fa9a50..b958b5b3c1 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -69,4 +69,42 @@ clocks = <&k3_clks 149 0>; clock-names = "fclk"; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721e-r5fss"; + lockstep-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721e-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <250>; + ti,sci-proc-ids = <0x01 0xFF>; + resets = <&k3_reset 250 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721e-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <251>; + ti,sci-proc-ids = <0x02 0xFF>; + resets = <&k3_reset 251 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; };