[U-Boot,v2,38/53] clk: sunxi: Implement SPI resets

Message ID	20180810060711.6547-39-jagan@amarulasolutions.com
State	Superseded
Delegated to:	Jagannadha Sutradharudu Teki
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Jagan Teki <jagan@amarulasolutions.com> To: Maxime Ripard <maxime.ripard@bootlin.com>, Andre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>, Icenowy Zheng <icenowy@aosc.io> Date: Fri, 10 Aug 2018 11:36:56 +0530 Message-Id: <20180810060711.6547-39-jagan@amarulasolutions.com> In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com> References: <20180810060711.6547-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 38/53] clk: sunxi: Implement SPI resets Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	clk: Add Allwinner CLK, RESET support \| expand [U-Boot,v2,00/53] clk: Add Allwinner CLK, RESET support [U-Boot,v2,01/53] clk: Kconfig: Ascending order to sub directiory kconfigs [U-Boot,v2,02/53] clk: Add Allwinner A64 CLK driver [U-Boot,v2,03/53] reset: Add default request ops [U-Boot,v2,04/53] reset: Add Allwinner RESET driver [U-Boot,v2,05/53] clk: sunxi: Add Allwinner H3/H5 CLK driver [U-Boot,v2,06/53] clk: sunxi: Add Allwinner A10/A20 CLK driver [U-Boot,v2,07/53] clk: sunxi: Add Allwinner A10s/A13 CLK driver [U-Boot,v2,08/53] clk: sunxi: Add Allwinner A31 CLK driver [U-Boot,v2,09/53] clk: sunxi: Add Allwinner A23 CLK driver [U-Boot,v2,10/53] clk: sunxi: a23: Add CLK support for A33 [U-Boot,v2,11/53] clk: sunxi: Add Allwinner A83T CLK driver [U-Boot,v2,12/53] clk: sunxi: Add Allwinner R40 CLK driver [U-Boot,v2,13/53] clk: sunxi: Add Allwinner V3S CLK driver [U-Boot,v2,14/53] sunxi: Enable CLK [U-Boot,v2,15/53] musb-new: sunxi: Use CLK and RESET support [U-Boot,v2,16/53] phy: sun4i-usb: Use CLK and RESET support [U-Boot,v2,17/53] sunxi: usb: Switch to Generic host controllers [U-Boot,v2,18/53] usb: host: Drop [e-o]hci-sunxi drivers [U-Boot,v2,19/53] clk: sunxi: Implement AHB bus MMC clocks [U-Boot,v2,20/53] clk: sunxi: Implement direct MMC clocks [U-Boot,v2,21/53] clk: sunxi: Implement AHB bus MMC resets [U-Boot,v2,22/53] reset: Add get reset by name optionally [U-Boot,v2,23/53] reset: Add reset valid [U-Boot,v2,24/53] dm: mmc: sunxi: Add CLK and RESET support [U-Boot,v2,25/53] fastboot: sunxi: Update fastboot mmc default device [U-Boot,v2,26/53] env: sunxi: Update default env fat device [U-Boot,v2,27/53] sunxi: Use mmc_bootdev=2 for MMC2 boot [U-Boot,v2,28/53] sunxi: A20: Enable DM_MMC [U-Boot,v2,29/53] mmc: sunxi: Add mmc, emmc H5/A64 compatible [U-Boot,v2,30/53] sunxi: H3_H5: Enable DM_MMC [U-Boot,v2,31/53] sunxi: A64: Enable DM_MMC [U-Boot,v2,32/53] mmc: sunxi: Add A83T emmc compatible [U-Boot,v2,33/53] sunxi: A83T: Enable DM_MMC [U-Boot,v2,34/53] sunxi: V40: Enable DM_MMC [U-Boot,v2,35/53] sunxi: A13/A31: Enable DM_MMC [U-Boot,v2,36/53] sunxi: A23/A33/V3S: Enable DM_MMC [U-Boot,v2,37/53] clk: sunxi: Implement SPI clocks [U-Boot,v2,38/53] clk: sunxi: Implement SPI resets [U-Boot,v2,39/53] spi: sun4i: Add CLK support [U-Boot,v2,40/53] spi: Add Allwinner A31 SPI driver [U-Boot,v2,41/53] clk: sunxi: Implement UART clocks [U-Boot,v2,42/53] clk: sunxi: Implement UART resets [U-Boot,v2,43/53] clk: sunxi: Implement Ethernet clocks [U-Boot,v2,44/53] clk: sunxi: Implement Ethernet resets [U-Boot,v2,45/53] net: sunxi_emac: Add CLK support [U-Boot,v2,46/53] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle [U-Boot,v2,47/53] net: sun8i_emac: Add CLK and RESET support [U-Boot,v2,48/53] clk: Get the CLK by index without device [U-Boot,v2,49/53] clk: Use clk_get_by_index_tail() [U-Boot,v2,50/53] reset: Get the RESET by index without device [U-Boot,v2,51/53] clk: sunxi: h3: Implement EPHY CLK and RESET [U-Boot,v2,52/53] net: sun8i_emac: Add EPHY CLK and RESET support [U-Boot,v2,53/53] board: sunxi: gmac: Remove Ethernet clock and reset

Message ID

20180810060711.6547-39-jagan@amarulasolutions.com

State

Superseded

Delegated to:

Jagannadha Sutradharudu Teki

Headers

From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
	Andre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,
	Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 10 Aug 2018 11:36:56 +0530
Message-Id: <20180810060711.6547-39-jagan@amarulasolutions.com>
In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com>
References: <20180810060711.6547-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
Cc: Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 38/53] clk: sunxi: Implement SPI resets
Precedence: list
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

clk: Add Allwinner CLK, RESET support | expand

Commit Message

Jagan Teki Aug. 10, 2018, 6:06 a.m. UTC

Implement SPI resets for all relevant Allwinner SoC
clock drivers via reset map descriptor table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a31.c | 4 ++++
 drivers/clk/sunxi/clk_a64.c | 2 ++
 drivers/clk/sunxi/clk_h3.c  | 2 ++
 drivers/clk/sunxi/clk_v3s.c | 1 +
 4 files changed, 9 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 1fa77e1272..a5c6628c63 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -55,6 +55,10 @@  static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
+	[RST_AHB1_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_AHB1_SPI1]		= { 0x2c0, BIT(21) },
+	[RST_AHB1_SPI2]		= { 0x2c0, BIT(22) },
+	[RST_AHB1_SPI3]		= { 0x2c0, BIT(23) },
 	[RST_AHB1_OTG]		= { 0x2c0, BIT(24) },
 	[RST_AHB1_EHCI0]	= { 0x2c0, BIT(26) },
 	[RST_AHB1_EHCI1]	= { 0x2c0, BIT(27) },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index aa2e69d0a3..218d4f09ea 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -47,6 +47,8 @@  static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 386289b654..f610cee745 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -54,6 +54,8 @@  static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 1cca57e065..ae4f6ee066 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -34,6 +34,7 @@  static struct ccu_reset_map v3s_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 };

[U-Boot,v2,38/53] clk: sunxi: Implement SPI resets

Commit Message

Patch