@@ -63,6 +63,7 @@ static struct ccu_reset_map a31_resets[] = {
[RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
[RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
[RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
+ [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
[RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
[RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
[RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
@@ -54,6 +54,7 @@ static struct ccu_reset_map a64_resets[] = {
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
@@ -47,6 +47,7 @@ static struct ccu_reset_map a83t_resets[] = {
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
@@ -60,6 +60,7 @@ static struct ccu_reset_map h3_resets[] = {
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
@@ -66,6 +66,8 @@ static struct ccu_reset_map r40_resets[] = {
[RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
[RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
+ [RST_BUS_GMAC] = { 0x2c0, BIT(17) },
+
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
Implement Ethernet resets for all relevant Allwinner SoC clock drivers via reset map descriptor table. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/clk/sunxi/clk_a31.c | 1 + drivers/clk/sunxi/clk_a64.c | 1 + drivers/clk/sunxi/clk_a83t.c | 1 + drivers/clk/sunxi/clk_h3.c | 1 + drivers/clk/sunxi/clk_r40.c | 2 ++ 5 files changed, 6 insertions(+)