@@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = {
[CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
[CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },
+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_APB1_UART4] = { 0x06c, BIT(20), NULL },
+ [CLK_APB1_UART5] = { 0x06c, BIT(21), NULL },
+ [CLK_APB1_UART6] = { 0x06c, BIT(22), NULL },
+ [CLK_APB1_UART7] = { 0x06c, BIT(23), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = {
[CLK_AHB_SPI1] = { 0x060, BIT(21), NULL },
[CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL },
+
#ifdef CONFIG_MMC
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {
[CLK_BUS_EHCI] = { 0x060, BIT(26), NULL },
[CLK_BUS_OHCI] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+
#ifdef CONFIG_MMC
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
@@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = {
[CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL },
[CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_APB2_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_APB2_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_APB2_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_APB2_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_APB2_UART4] = { 0x06c, BIT(20), NULL },
+ [CLK_APB2_UART5] = { 0x06c, BIT(21), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = {
[CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL },
[CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = {
[CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL },
[CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = {
[CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL },
[CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = {
[CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL },
[CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+ [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL },
+ [CLK_BUS_UART5] = { 0x06c, BIT(21), NULL },
+ [CLK_BUS_UART6] = { 0x06c, BIT(22), NULL },
+ [CLK_BUS_UART7] = { 0x06c, BIT(23), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = {
[CLK_BUS_SPI0] = { 0x060, BIT(20), NULL },
[CLK_BUS_OTG] = { 0x060, BIT(24), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
+ [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
+ [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
Implement UART clocks for all Allwinner SoC clock drivers via clock map descriptor table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 5 +++++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 7 +++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_r40.c | 9 +++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 9 files changed, 57 insertions(+)