diff mbox series

[U-Boot,v5,07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code

Message ID 1570787542-40896-8-git-send-email-ley.foon.tan@intel.com
State Superseded
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Agilex SoC support | expand

Commit Message

Ley Foon Tan Oct. 11, 2019, 9:52 a.m. UTC 
Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

---
v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
 .../include/mach/clock_manager_s10.h          | 16 +++----------
 .../include/mach/clock_manager_soc64.h        | 23 +++++++++++++++++++
 2 files changed, 26 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h

Comments

Simon Goldschmidt Oct. 22, 2019, 6:29 p.m. UTC | #1 
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> Move Stratix10 and Agilex clock manager common code to new header file.
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> 
> ---
> v5:
> - Revert CLKMGR_INTOSC_HZ to 460MHz.
> ---
>   .../include/mach/clock_manager_s10.h          | 16 +++----------
>   .../include/mach/clock_manager_soc64.h        | 23 +++++++++++++++++++
>   2 files changed, 26 insertions(+), 13 deletions(-)
>   create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index fa0ba26f09..223940ba0c 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -1,6 +1,6 @@
>   /* SPDX-License-Identifier: GPL-2.0
>    *
> - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
>    *
>    */
>   
> @@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
>   unsigned int cm_get_mmc_controller_clk_hz(void);
>   unsigned int cm_get_qspi_controller_clk_hz(void);
>   unsigned int cm_get_spi_controller_clk_hz(void);
> -const unsigned int cm_get_osc_clk_hz(void);
> -const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> -const unsigned int cm_get_intosc_clk_hz(void);
> -const unsigned int cm_get_fpga_clk_hz(void);
> -
> -#define CLKMGR_EOSC1_HZ		25000000
> -#define CLKMGR_INTOSC_HZ	460000000
> -#define CLKMGR_FPGA_CLK_HZ	50000000
> -
> -/* Clock configuration accessors */
> -const struct cm_config * const cm_get_default_config(void);
>   
>   struct cm_config {
>   	/* main group */
> @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg);
>   
>   #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
>   
> +#include <asm/arch/clock_manager_soc64.h>

Includes are normally at the top, what prevents you from moving this up?

> +
>   #endif /* _CLOCK_MANAGER_S10_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> new file mode 100644
> index 0000000000..3b4bb62ca5
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef _CLOCK_MANAGER_SOC64_
> +#define _CLOCK_MANAGER_SOC64_
> +
> +const unsigned int cm_get_osc_clk_hz(void);
> +const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> +const unsigned int cm_get_intosc_clk_hz(void);
> +const unsigned int cm_get_fpga_clk_hz(void);
> +
> +#define CLKMGR_EOSC1_HZ		25000000
> +#define CLKMGR_INTOSC_HZ	460000000
> +#define CLKMGR_FPGA_CLK_HZ	50000000
> +
> +/* Clock configuration accessors */
> +const struct cm_config * const cm_get_default_config(void);
> +
> +#endif /* _CLOCK_MANAGER_SOC64_ */
>
Ley Foon Tan Oct. 25, 2019, 9:19 a.m. UTC | #2 
On Wed, Oct 23, 2019 at 2:29 AM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> > Move Stratix10 and Agilex clock manager common code to new header file.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> >
> > ---
> > v5:
> > - Revert CLKMGR_INTOSC_HZ to 460MHz.
> > ---
> >   .../include/mach/clock_manager_s10.h          | 16 +++----------
> >   .../include/mach/clock_manager_soc64.h        | 23 +++++++++++++++++++
> >   2 files changed, 26 insertions(+), 13 deletions(-)
> >   create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> > index fa0ba26f09..223940ba0c 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> > @@ -1,6 +1,6 @@
> >   /* SPDX-License-Identifier: GPL-2.0
> >    *
> > - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> > + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> >    *
> >    */
> >
> > @@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
> >   unsigned int cm_get_mmc_controller_clk_hz(void);
> >   unsigned int cm_get_qspi_controller_clk_hz(void);
> >   unsigned int cm_get_spi_controller_clk_hz(void);
> > -const unsigned int cm_get_osc_clk_hz(void);
> > -const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> > -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> > -const unsigned int cm_get_intosc_clk_hz(void);
> > -const unsigned int cm_get_fpga_clk_hz(void);
> > -
> > -#define CLKMGR_EOSC1_HZ              25000000
> > -#define CLKMGR_INTOSC_HZ     460000000
> > -#define CLKMGR_FPGA_CLK_HZ   50000000
> > -
> > -/* Clock configuration accessors */
> > -const struct cm_config * const cm_get_default_config(void);
> >
> >   struct cm_config {
> >       /* main group */
> > @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg);
> >
> >   #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK           0x00000020
> >
> > +#include <asm/arch/clock_manager_soc64.h>
>
> Includes are normally at the top, what prevents you from moving this up?
You are right, it should be at top. Will change it.

Thanks
Ley Foon
>
> > +
> >   #endif /* _CLOCK_MANAGER_S10_ */
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> > new file mode 100644
> > index 0000000000..3b4bb62ca5
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> > + *
> > + */
> > +
> > +#ifndef _CLOCK_MANAGER_SOC64_
> > +#define _CLOCK_MANAGER_SOC64_
> > +
> > +const unsigned int cm_get_osc_clk_hz(void);
> > +const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> > +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> > +const unsigned int cm_get_intosc_clk_hz(void);
> > +const unsigned int cm_get_fpga_clk_hz(void);
> > +
> > +#define CLKMGR_EOSC1_HZ              25000000
> > +#define CLKMGR_INTOSC_HZ     460000000
> > +#define CLKMGR_FPGA_CLK_HZ   50000000
> > +
> > +/* Clock configuration accessors */
> > +const struct cm_config * const cm_get_default_config(void);
> > +
> > +#endif /* _CLOCK_MANAGER_SOC64_ */
> >
>
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index fa0ba26f09..223940ba0c 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,6 +1,6 @@ 
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
  *
  */
 
@@ -14,18 +14,6 @@  unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(void);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-const unsigned int cm_get_intosc_clk_hz(void);
-const unsigned int cm_get_fpga_clk_hz(void);
-
-#define CLKMGR_EOSC1_HZ		25000000
-#define CLKMGR_INTOSC_HZ	460000000
-#define CLKMGR_FPGA_CLK_HZ	50000000
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
 
 struct cm_config {
 	/* main group */
@@ -186,4 +174,6 @@  void cm_basic_init(const struct cm_config * const cfg);
 
 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
 
+#include <asm/arch/clock_manager_soc64.h>
+
 #endif /* _CLOCK_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 0000000000..3b4bb62ca5
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,23 @@ 
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ		25000000
+#define CLKMGR_INTOSC_HZ	460000000
+#define CLKMGR_FPGA_CLK_HZ	50000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */