From patchwork Fri Oct 11 09:52:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1175103 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46qNn45y9Pz9sNx for ; Fri, 11 Oct 2019 21:03:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7FD1BC21D74; Fri, 11 Oct 2019 09:54:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C36BC21CB1; Fri, 11 Oct 2019 09:53:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B9808C21E2F; Fri, 11 Oct 2019 09:53:08 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lists.denx.de (Postfix) with ESMTPS id 004E1C21E53 for ; Fri, 11 Oct 2019 09:53:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 02:53:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,283,1566889200"; d="scan'208";a="394362882" Received: from unknown (HELO ubuntu) ([10.226.248.89]) by fmsmga005.fm.intel.com with SMTP; 11 Oct 2019 02:52:56 -0700 Received: by ubuntu (sSMTP sendmail emulation); Fri, 11 Oct 2019 17:52:56 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Date: Fri, 11 Oct 2019 17:52:10 +0800 Message-Id: <1570787542-40896-8-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570787542-40896-1-git-send-email-ley.foon.tan@intel.com> References: <1570787542-40896-1-git-send-email-ley.foon.tan@intel.com> Cc: Marek Vasut , Tien Fong Chee , Chin Liang See , Chee Hong Ang Subject: [U-Boot] [PATCH v5 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan --- v5: - Revert CLKMGR_INTOSC_HZ to 460MHz. --- .../include/mach/clock_manager_s10.h | 16 +++---------- .../include/mach/clock_manager_soc64.h | 23 +++++++++++++++++++ 2 files changed, 26 insertions(+), 13 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index fa0ba26f09..223940ba0c 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2019 Intel Corporation * */ @@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); -const unsigned int cm_get_osc_clk_hz(void); -const unsigned int cm_get_f2s_per_ref_clk_hz(void); -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); -const unsigned int cm_get_intosc_clk_hz(void); -const unsigned int cm_get_fpga_clk_hz(void); - -#define CLKMGR_EOSC1_HZ 25000000 -#define CLKMGR_INTOSC_HZ 460000000 -#define CLKMGR_FPGA_CLK_HZ 50000000 - -/* Clock configuration accessors */ -const struct cm_config * const cm_get_default_config(void); struct cm_config { /* main group */ @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 +#include + #endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h new file mode 100644 index 0000000000..3b4bb62ca5 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2019 Intel Corporation + * + */ + +#ifndef _CLOCK_MANAGER_SOC64_ +#define _CLOCK_MANAGER_SOC64_ + +const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void); + +#define CLKMGR_EOSC1_HZ 25000000 +#define CLKMGR_INTOSC_HZ 460000000 +#define CLKMGR_FPGA_CLK_HZ 50000000 + +/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void); + +#endif /* _CLOCK_MANAGER_SOC64_ */