diff mbox series

[57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector

Message ID 20240412073735.76413-58-eric.huang@linux.alibaba.com
State New
Headers show
Series target/riscv: Support XTheadVector extension | expand

Commit Message

Huang Tao April 12, 2024, 7:37 a.m. UTC 
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
 target/riscv/helper.h                         |  4 ++
 .../riscv/insn_trans/trans_xtheadvector.c.inc | 36 ++++++++++-
 target/riscv/xtheadvector_helper.c            | 64 +++++++++++++++++++
 3 files changed, 101 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2379a3431d..90a1ff2601 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2302,3 +2302,7 @@  DEF_HELPER_6(th_vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_4(th_vmpopc_m, tl, ptr, ptr, env, i32)
 
 DEF_HELPER_4(th_vmfirst_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_5(th_vmsbf_m, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vmsif_m, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vmsof_m, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 45554c38fb..d41c691c31 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2500,6 +2500,39 @@  static bool trans_th_vmfirst_m(DisasContext *s, arg_rmr *a)
     }
     return false;
 }
+/*
+ * th.vmsbf.m set-before-first mask bit
+ * th.vmsif.m set-including-first mask bit
+ * th.vmsof.m set-only-first mask bit
+ */
+#define GEN_M_TRANS_TH(NAME)                                       \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
+{                                                                  \
+    if (require_xtheadvector(s) &&                                 \
+        vext_check_isa_ill(s) &&                                   \
+        (a->rd != a->rs2) &&                                       \
+        s->vstart_eq_zero) {                                       \
+        uint32_t data = 0;                                         \
+        gen_helper_gvec_3_ptr *fn = gen_helper_##NAME;             \
+                                                                   \
+        data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);          \
+        data = FIELD_DP32(data, VDATA_TH, VM, a->vm);              \
+        data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);          \
+        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
+                           vreg_ofs(s, 0),                         \
+                           vreg_ofs(s, a->rs2),                    \
+                           tcg_env, s->cfg_ptr->vlenb,             \
+                           s->cfg_ptr->vlenb,                      \
+                           data, fn);                              \
+        finalize_rvv_inst(s);                                      \
+        return true;                                               \
+    }                                                              \
+    return false;                                                  \
+}
+
+GEN_M_TRANS_TH(th_vmsbf_m)
+GEN_M_TRANS_TH(th_vmsif_m)
+GEN_M_TRANS_TH(th_vmsof_m)
 
 #define TH_TRANS_STUB(NAME)                                \
 static bool trans_##NAME(DisasContext *s, arg_##NAME *a)   \
@@ -2507,9 +2540,6 @@  static bool trans_##NAME(DisasContext *s, arg_##NAME *a)   \
     return require_xtheadvector(s);                        \
 }
 
-TH_TRANS_STUB(th_vmsbf_m)
-TH_TRANS_STUB(th_vmsif_m)
-TH_TRANS_STUB(th_vmsof_m)
 TH_TRANS_STUB(th_viota_m)
 TH_TRANS_STUB(th_vid_v)
 TH_TRANS_STUB(th_vext_x_v)
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 1860e47f4f..d4f1665bf3 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3558,3 +3558,67 @@  target_ulong HELPER(th_vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
     env->vstart = 0;
     return -1LL;
 }
+
+enum set_mask_type_th {
+    ONLY_FIRST = 1,
+    INCLUDE_FIRST,
+    BEFORE_FIRST,
+};
+
+static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
+                   uint32_t desc, enum set_mask_type_th type)
+{
+    uint32_t mlen = th_mlen(desc);
+    uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen;
+    uint32_t vm = th_vm(desc);
+    uint32_t vl = env->vl;
+    int i;
+    bool first_mask_bit = false;
+
+    for (i = env->vstart; i < vl; i++) {
+        if (!vm && !th_elem_mask(v0, mlen, i)) {
+            continue;
+        }
+        /* write a zero to all following active elements */
+        if (first_mask_bit) {
+            th_set_elem_mask(vd, mlen, i, 0);
+            continue;
+        }
+        if (th_elem_mask(vs2, mlen, i)) {
+            first_mask_bit = true;
+            if (type == BEFORE_FIRST) {
+                th_set_elem_mask(vd, mlen, i, 0);
+            } else {
+                th_set_elem_mask(vd, mlen, i, 1);
+            }
+        } else {
+            if (type == ONLY_FIRST) {
+                th_set_elem_mask(vd, mlen, i, 0);
+            } else {
+                th_set_elem_mask(vd, mlen, i, 1);
+            }
+        }
+    }
+    env->vstart = 0;
+    for (; i < vlmax; i++) {
+        th_set_elem_mask(vd, mlen, i, 0);
+    }
+}
+
+void HELPER(th_vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+                        uint32_t desc)
+{
+    vmsetm(vd, v0, vs2, env, desc, BEFORE_FIRST);
+}
+
+void HELPER(th_vmsif_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+                        uint32_t desc)
+{
+    vmsetm(vd, v0, vs2, env, desc, INCLUDE_FIRST);
+}
+
+void HELPER(th_vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
+                        uint32_t desc)
+{
+    vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST);
+}