diff mbox series

[56/65] target/riscv: Add th.vmfirst.m for XTheadVector

Message ID 20240412073735.76413-57-eric.huang@linux.alibaba.com
State New
Headers show
Series target/riscv: Support XTheadVector extension | expand

Commit Message

Huang Tao April 12, 2024, 7:37 a.m. UTC 
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
 target/riscv/helper.h                         |  2 ++
 .../riscv/insn_trans/trans_xtheadvector.c.inc | 31 ++++++++++++++++++-
 target/riscv/xtheadvector_helper.c            | 20 ++++++++++++
 3 files changed, 52 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6ddecbbe65..2379a3431d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2300,3 +2300,5 @@  DEF_HELPER_6(th_vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(th_vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
 
 DEF_HELPER_4(th_vmpopc_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_4(th_vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index f8e8b321e4..45554c38fb 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2471,13 +2471,42 @@  static bool trans_th_vmpopc_m(DisasContext *s, arg_rmr *a)
     return false;
 }
 
+/* vmfirst find-first-set mask bit */
+static bool trans_th_vmfirst_m(DisasContext *s, arg_rmr *a)
+{
+    if (require_xtheadvector(s) &&
+        vext_check_isa_ill(s)) {
+        TCGv_ptr src2, mask;
+        TCGv dst;
+        TCGv_i32 desc;
+        uint32_t data = 0;
+        data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);
+        data = FIELD_DP32(data, VDATA_TH, VM, a->vm);
+        data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);
+
+        mask = tcg_temp_new_ptr();
+        src2 = tcg_temp_new_ptr();
+        dst = dest_gpr(s, a->rd);
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+                                          s->cfg_ptr->vlenb, data));
+
+        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
+        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
+
+        gen_helper_th_vmfirst_m(dst, mask, src2, tcg_env, desc);
+        gen_set_gpr(s, a->rd, dst);
+
+        return true;
+    }
+    return false;
+}
+
 #define TH_TRANS_STUB(NAME)                                \
 static bool trans_##NAME(DisasContext *s, arg_##NAME *a)   \
 {                                                          \
     return require_xtheadvector(s);                        \
 }
 
-TH_TRANS_STUB(th_vmfirst_m)
 TH_TRANS_STUB(th_vmsbf_m)
 TH_TRANS_STUB(th_vmsif_m)
 TH_TRANS_STUB(th_vmsof_m)
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index ba1ab0435d..1860e47f4f 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3538,3 +3538,23 @@  target_ulong HELPER(th_vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
     env->vstart = 0;
     return cnt;
 }
+
+/* vmfirst find-first-set mask bit*/
+target_ulong HELPER(th_vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+                               uint32_t desc)
+{
+    uint32_t mlen = th_mlen(desc);
+    uint32_t vm = th_vm(desc);
+    uint32_t vl = env->vl;
+    int i;
+
+    for (i = env->vstart; i < vl; i++) {
+        if (vm || th_elem_mask(v0, mlen, i)) {
+            if (th_elem_mask(vs2, mlen, i)) {
+                return i;
+            }
+        }
+    }
+    env->vstart = 0;
+    return -1LL;
+}