diff mbox series

[44/65] target/riscv: Add floating-point sign-injection instructions for XTheadVector

Message ID 20240412073735.76413-45-eric.huang@linux.alibaba.com
State New
Headers show
Series target/riscv: Support XTheadVector extension | expand

Commit Message

Huang Tao April 12, 2024, 7:37 a.m. UTC 
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
 target/riscv/helper.h                         | 19 +++++++++
 .../riscv/insn_trans/trans_xtheadvector.c.inc | 14 ++++---
 target/riscv/vector_helper.c                  | 18 ++++----
 target/riscv/vector_internals.h               | 10 +++++
 target/riscv/xtheadvector_helper.c            | 41 +++++++++++++++++++
 5 files changed, 87 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 86ae984430..2b9d7fa2b6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2133,3 +2133,22 @@  DEF_HELPER_6(th_vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32)
 DEF_HELPER_6(th_vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32)
 DEF_HELPER_6(th_vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32)
 DEF_HELPER_6(th_vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(th_vfsgnj_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnj_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnj_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjx_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjx_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjx_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnj_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnj_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnj_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjn_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjn_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjn_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index d3205ce2a0..1374bad5b9 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2098,18 +2098,20 @@  GEN_OPFVV_TRANS_TH(th_vfmax_vv, opfvv_check_th)
 GEN_OPFVF_TRANS_TH(th_vfmin_vf, opfvf_check_th)
 GEN_OPFVF_TRANS_TH(th_vfmax_vf, opfvf_check_th)
 
+/* Vector Floating-Point Sign-Injection Instructions */
+GEN_OPFVV_TRANS_TH(th_vfsgnj_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfsgnjn_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfsgnjx_vv, opfvv_check_th)
+GEN_OPFVF_TRANS_TH(th_vfsgnj_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfsgnjn_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfsgnjx_vf, opfvf_check_th)
+
 #define TH_TRANS_STUB(NAME)                                \
 static bool trans_##NAME(DisasContext *s, arg_##NAME *a)   \
 {                                                          \
     return require_xtheadvector(s);                        \
 }
 
-TH_TRANS_STUB(th_vfsgnj_vv)
-TH_TRANS_STUB(th_vfsgnj_vf)
-TH_TRANS_STUB(th_vfsgnjn_vv)
-TH_TRANS_STUB(th_vfsgnjn_vf)
-TH_TRANS_STUB(th_vfsgnjx_vv)
-TH_TRANS_STUB(th_vfsgnjx_vf)
 TH_TRANS_STUB(th_vmfeq_vv)
 TH_TRANS_STUB(th_vmfeq_vf)
 TH_TRANS_STUB(th_vmfne_vv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ef89794bdd..d0ebda5445 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3882,17 +3882,17 @@  GEN_VEXT_VF(vfmax_vf_w, 4)
 GEN_VEXT_VF(vfmax_vf_d, 8)
 
 /* Vector Floating-Point Sign-Injection Instructions */
-static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
+uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
 {
     return deposit64(b, 0, 15, a);
 }
 
-static uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s)
+uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s)
 {
     return deposit64(b, 0, 31, a);
 }
 
-static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
+uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
 {
     return deposit64(b, 0, 63, a);
 }
@@ -3910,17 +3910,17 @@  GEN_VEXT_VF(vfsgnj_vf_h, 2)
 GEN_VEXT_VF(vfsgnj_vf_w, 4)
 GEN_VEXT_VF(vfsgnj_vf_d, 8)
 
-static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
+uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
 {
     return deposit64(~b, 0, 15, a);
 }
 
-static uint32_t fsgnjn32(uint32_t a, uint32_t b, float_status *s)
+uint32_t fsgnjn32(uint32_t a, uint32_t b, float_status *s)
 {
     return deposit64(~b, 0, 31, a);
 }
 
-static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
+uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
 {
     return deposit64(~b, 0, 63, a);
 }
@@ -3938,17 +3938,17 @@  GEN_VEXT_VF(vfsgnjn_vf_h, 2)
 GEN_VEXT_VF(vfsgnjn_vf_w, 4)
 GEN_VEXT_VF(vfsgnjn_vf_d, 8)
 
-static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
+uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
 {
     return deposit64(b ^ a, 0, 15, a);
 }
 
-static uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s)
+uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s)
 {
     return deposit64(b ^ a, 0, 31, a);
 }
 
-static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
+uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
 {
     return deposit64(b ^ a, 0, 63, a);
 }
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 535d31007d..bcc7d0edd6 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -394,4 +394,14 @@  uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s);
 uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s);
 uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s);
 
+uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s);
+uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s);
+uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s);
+uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s);
+uint32_t fsgnjn32(uint32_t a, uint32_t b, float_status *s);
+uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s);
+uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s);
+uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s);
+uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s);
+
 #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 5593cace78..38476900a6 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3010,3 +3010,44 @@  THCALL(TH_OPFVF2, th_vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
 GEN_TH_VF(th_vfmax_vf_h, 2, 2, clearh_th)
 GEN_TH_VF(th_vfmax_vf_w, 4, 4, clearl_th)
 GEN_TH_VF(th_vfmax_vf_d, 8, 8, clearq_th)
+
+/* Vector Floating-Point Sign-Injection Instructions */
+
+THCALL(TH_OPFVV2, th_vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
+THCALL(TH_OPFVV2, th_vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
+THCALL(TH_OPFVV2, th_vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
+GEN_TH_VV_ENV(th_vfsgnj_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfsgnj_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfsgnj_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF2, th_vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
+THCALL(TH_OPFVF2, th_vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
+THCALL(TH_OPFVF2, th_vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
+GEN_TH_VF(th_vfsgnj_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfsgnj_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfsgnj_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV2, th_vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
+THCALL(TH_OPFVV2, th_vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
+THCALL(TH_OPFVV2, th_vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
+GEN_TH_VV_ENV(th_vfsgnjn_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfsgnjn_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfsgnjn_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF2, th_vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
+THCALL(TH_OPFVF2, th_vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
+THCALL(TH_OPFVF2, th_vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
+GEN_TH_VF(th_vfsgnjn_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfsgnjn_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfsgnjn_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV2, th_vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
+THCALL(TH_OPFVV2, th_vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
+THCALL(TH_OPFVV2, th_vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
+GEN_TH_VV_ENV(th_vfsgnjx_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfsgnjx_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfsgnjx_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF2, th_vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
+THCALL(TH_OPFVF2, th_vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
+THCALL(TH_OPFVF2, th_vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
+GEN_TH_VF(th_vfsgnjx_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfsgnjx_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfsgnjx_vf_d, 8, 8, clearq_th)