@@ -2298,3 +2298,5 @@ DEF_HELPER_6(th_vmor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_4(th_vmpopc_m, tl, ptr, ptr, env, i32)
@@ -2441,13 +2441,42 @@ GEN_MM_TRANS_TH(th_vmnor_mm)
GEN_MM_TRANS_TH(th_vmornot_mm)
GEN_MM_TRANS_TH(th_vmxnor_mm)
+/* Vector mask population count vmpopc */
+static bool trans_th_vmpopc_m(DisasContext *s, arg_rmr *a)
+{
+ if (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ s->vstart_eq_zero) {
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm);
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);
+
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = dest_gpr(s, a->rd);
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
+
+ tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
+
+ gen_helper_th_vmpopc_m(dst, mask, src2, tcg_env, desc);
+ gen_set_gpr(s, a->rd, dst);
+ return true;
+ }
+ return false;
+}
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vmpopc_m)
TH_TRANS_STUB(th_vmfirst_m)
TH_TRANS_STUB(th_vmsbf_m)
TH_TRANS_STUB(th_vmsif_m)
@@ -3517,3 +3517,24 @@ GEN_TH_MASK_VV(th_vmor_mm, TH_OR)
GEN_TH_MASK_VV(th_vmnor_mm, TH_NOR)
GEN_TH_MASK_VV(th_vmornot_mm, TH_ORNOT)
GEN_TH_MASK_VV(th_vmxnor_mm, TH_XNOR)
+
+/* Vector mask population count vmpopc */
+target_ulong HELPER(th_vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+ target_ulong cnt = 0;
+ uint32_t mlen = th_mlen(desc);
+ uint32_t vm = th_vm(desc);
+ uint32_t vl = env->vl;
+ int i;
+
+ for (i = env->vstart; i < vl; i++) {
+ if (vm || th_elem_mask(v0, mlen, i)) {
+ if (th_elem_mask(vs2, mlen, i)) {
+ cnt++;
+ }
+ }
+ }
+ env->vstart = 0;
+ return cnt;
+}
The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com> --- target/riscv/helper.h | 2 ++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 31 ++++++++++++++++++- target/riscv/xtheadvector_helper.c | 21 +++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-)