| Message ID | 20230213180215.1524938-6-bmeng@tinylab.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Various fixes to gdbstub and CSR access | expand |
On 2023/2/14 02:02, Bin Meng wrote: > Fix various places that violate QEMU coding style: > > - correct multi-line comment format > - indent to opening parenthesis > > Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > --- > > target/riscv/csr.c | 62 ++++++++++++++++++++++++---------------------- > 1 file changed, 32 insertions(+), 30 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index c2dd9d5af0..cc74819759 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno) > } > > static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->vstimecmp; > > @@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->vstimecmp >> 32; > > @@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, > } > > static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException read_stimecmph(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > if (riscv_cpu_virt_enabled(env)) { > *val = env->vstimecmp >> 32; > @@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno, > } > > static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, > > /* 'E' excludes all other extensions */ > if (val & RVE) { > - /* when we support 'E' we can do "val = RVE;" however > + /* > + * when we support 'E' we can do "val = RVE;" however > * for now we just drop writes if 'E' is present. > */ > return RISCV_EXCP_NONE; > @@ -1364,7 +1365,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, > val &= ~RVD; > } > > - /* Suppress 'C' if next instruction is not aligned > + /* > + * Suppress 'C' if next instruction is not aligned > * TODO: this should check next_pc > */ > if ((val & RVC) && (GETPC() & ~3) != 0) { > @@ -1833,28 +1835,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno, > } > > static RISCVException read_mepc(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->mepc; > return RISCV_EXCP_NONE; > } > > static RISCVException write_mepc(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > env->mepc = val; > return RISCV_EXCP_NONE; > } > > static RISCVException read_mcause(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->mcause; > return RISCV_EXCP_NONE; > } > > static RISCVException write_mcause(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > env->mcause = val; > return RISCV_EXCP_NONE; > @@ -1876,14 +1878,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, > > /* Execution environment configuration setup */ > static RISCVException read_menvcfg(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->menvcfg; > return RISCV_EXCP_NONE; > } > > static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; > > @@ -1896,14 +1898,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->menvcfg >> 32; > return RISCV_EXCP_NONE; > } > > static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; > uint64_t valh = (uint64_t)val << 32; > @@ -1914,7 +1916,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > } > > static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > RISCVException ret; > > @@ -1928,7 +1930,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; > RISCVException ret; > @@ -1943,7 +1945,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > RISCVException ret; > > @@ -1957,7 +1959,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; > RISCVException ret; > @@ -1977,7 +1979,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > RISCVException ret; > > @@ -1991,7 +1993,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > } > > static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; > uint64_t valh = (uint64_t)val << 32; > @@ -2034,13 +2036,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > } > > static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > } > > static RISCVException read_mstateenh(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; > > @@ -2061,7 +2063,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, > } > > static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > @@ -2069,7 +2071,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > } > > static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > } > @@ -2106,7 +2108,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > } > > static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > } > @@ -2145,7 +2147,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > } > > static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > } > @@ -3338,7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno, > } > > static RISCVException write_mseccfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > mseccfg_csr_write(env, val); > return RISCV_EXCP_NONE;
On 2023/2/14 2:02, Bin Meng wrote: > Fix various places that violate QEMU coding style: > > - correct multi-line comment format > - indent to opening parenthesis > > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > target/riscv/csr.c | 62 ++++++++++++++++++++++++---------------------- > 1 file changed, 32 insertions(+), 30 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index c2dd9d5af0..cc74819759 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno) > } > > static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->vstimecmp; > > @@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->vstimecmp >> 32; > > @@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, > } > > static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException read_stimecmph(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > if (riscv_cpu_virt_enabled(env)) { > *val = env->vstimecmp >> 32; > @@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno, > } > > static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > } > > static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > RISCVCPU *cpu = env_archcpu(env); > > @@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, > > /* 'E' excludes all other extensions */ > if (val & RVE) { > - /* when we support 'E' we can do "val = RVE;" however > + /* > + * when we support 'E' we can do "val = RVE;" however > * for now we just drop writes if 'E' is present. > */ > return RISCV_EXCP_NONE; > @@ -1364,7 +1365,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, > val &= ~RVD; > } > > - /* Suppress 'C' if next instruction is not aligned > + /* > + * Suppress 'C' if next instruction is not aligned > * TODO: this should check next_pc > */ > if ((val & RVC) && (GETPC() & ~3) != 0) { > @@ -1833,28 +1835,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno, > } > > static RISCVException read_mepc(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->mepc; > return RISCV_EXCP_NONE; > } > > static RISCVException write_mepc(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > env->mepc = val; > return RISCV_EXCP_NONE; > } > > static RISCVException read_mcause(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->mcause; > return RISCV_EXCP_NONE; > } > > static RISCVException write_mcause(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > env->mcause = val; > return RISCV_EXCP_NONE; > @@ -1876,14 +1878,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, > > /* Execution environment configuration setup */ > static RISCVException read_menvcfg(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->menvcfg; > return RISCV_EXCP_NONE; > } > > static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; > > @@ -1896,14 +1898,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->menvcfg >> 32; > return RISCV_EXCP_NONE; > } > > static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; > uint64_t valh = (uint64_t)val << 32; > @@ -1914,7 +1916,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > } > > static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > RISCVException ret; > > @@ -1928,7 +1930,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; > RISCVException ret; > @@ -1943,7 +1945,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > RISCVException ret; > > @@ -1957,7 +1959,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; > RISCVException ret; > @@ -1977,7 +1979,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > } > > static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > RISCVException ret; > > @@ -1991,7 +1993,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > } > > static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) > { > uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; > uint64_t valh = (uint64_t)val << 32; > @@ -2034,13 +2036,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > } > > static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > } > > static RISCVException read_mstateenh(CPURISCVState *env, int csrno, > - target_ulong *val) > + target_ulong *val) > { > *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; > > @@ -2061,7 +2063,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, > } > > static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > @@ -2069,7 +2071,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > } > > static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > } > @@ -2106,7 +2108,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > } > > static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > } > @@ -2145,7 +2147,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > } > > static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, > - target_ulong new_val) > + target_ulong new_val) > { > return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > } > @@ -3338,7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno, > } > > static RISCVException write_mseccfg(CPURISCVState *env, int csrno, > - target_ulong val) > + target_ulong val) Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > { > mseccfg_csr_write(env, val); > return RISCV_EXCP_NONE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c2dd9d5af0..cc74819759 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno) } static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->vstimecmp; @@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, } static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->vstimecmp >> 32; @@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, } static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { RISCVCPU *cpu = env_archcpu(env); @@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, } static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { RISCVCPU *cpu = env_archcpu(env); @@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno, } static RISCVException read_stimecmph(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { if (riscv_cpu_virt_enabled(env)) { *val = env->vstimecmp >> 32; @@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno, } static RISCVException write_stimecmp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { RISCVCPU *cpu = env_archcpu(env); @@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, } static RISCVException write_stimecmph(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { RISCVCPU *cpu = env_archcpu(env); @@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, /* 'E' excludes all other extensions */ if (val & RVE) { - /* when we support 'E' we can do "val = RVE;" however + /* + * when we support 'E' we can do "val = RVE;" however * for now we just drop writes if 'E' is present. */ return RISCV_EXCP_NONE; @@ -1364,7 +1365,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= ~RVD; } - /* Suppress 'C' if next instruction is not aligned + /* + * Suppress 'C' if next instruction is not aligned * TODO: this should check next_pc */ if ((val & RVC) && (GETPC() & ~3) != 0) { @@ -1833,28 +1835,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno, } static RISCVException read_mepc(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->mepc; return RISCV_EXCP_NONE; } static RISCVException write_mepc(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { env->mepc = val; return RISCV_EXCP_NONE; } static RISCVException read_mcause(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->mcause; return RISCV_EXCP_NONE; } static RISCVException write_mcause(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { env->mcause = val; return RISCV_EXCP_NONE; @@ -1876,14 +1878,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, /* Execution environment configuration setup */ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->menvcfg; return RISCV_EXCP_NONE; } static RISCVException write_menvcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; @@ -1896,14 +1898,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, } static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->menvcfg >> 32; return RISCV_EXCP_NONE; } static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; uint64_t valh = (uint64_t)val << 32; @@ -1914,7 +1916,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, } static RISCVException read_senvcfg(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { RISCVException ret; @@ -1928,7 +1930,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno, } static RISCVException write_senvcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; RISCVException ret; @@ -1943,7 +1945,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, } static RISCVException read_henvcfg(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { RISCVException ret; @@ -1957,7 +1959,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, } static RISCVException write_henvcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; RISCVException ret; @@ -1977,7 +1979,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, } static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { RISCVException ret; @@ -1991,7 +1993,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, } static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh = (uint64_t)val << 32; @@ -2034,13 +2036,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, } static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val) { return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); } static RISCVException read_mstateenh(CPURISCVState *env, int csrno, - target_ulong *val) + target_ulong *val) { *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; @@ -2061,7 +2063,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, } static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val) { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; @@ -2069,7 +2071,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, } static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val) { return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -2106,7 +2108,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, } static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val) { return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -2145,7 +2147,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, } static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val) { return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -3338,7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno, } static RISCVException write_mseccfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val) { mseccfg_csr_write(env, val); return RISCV_EXCP_NONE;
Fix various places that violate QEMU coding style: - correct multi-line comment format - indent to opening parenthesis Signed-off-by: Bin Meng <bmeng@tinylab.org> --- target/riscv/csr.c | 62 ++++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 30 deletions(-)