| Message ID | 20230213180215.1524938-9-bmeng@tinylab.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Various fixes to gdbstub and CSR access | expand |
On 2023/2/14 02:02, Bin Meng wrote: > Use env_archcpu() to get RISCVCPU pointer from env directly. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > --- > > target/riscv/csr.c | 36 ++++++++++++------------------------ > 1 file changed, 12 insertions(+), 24 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index da3b770894..0a3f2bef6f 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, > uint64_t bit) > { > bool virt = riscv_cpu_virt_enabled(env); > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { > return RISCV_EXCP_NONE; > @@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) > > static RISCVException vs(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (env->misa_ext & RVV || > cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { > @@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno) > static RISCVException ctr(CPURISCVState *env, int csrno) > { > #if !defined(CONFIG_USER_ONLY) > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > int ctr_index; > target_ulong ctr_mask; > int base_csrno = CSR_CYCLE; > @@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno) > #if !defined(CONFIG_USER_ONLY) > static RISCVException mctr(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > int ctr_index; > int base_csrno = CSR_MHPMCOUNTER3; > > @@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno) > > static RISCVException sscofpmf(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_sscofpmf) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno) > > static RISCVException mstateen(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno) > > static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno) > { > bool virt = riscv_cpu_virt_enabled(env); > int index = csrno - CSR_SSTATEEN0; > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, > > static RISCVException sstc(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > bool hmode_check = false; > > if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { > @@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno, > static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > target_ulong *val) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > *val = cpu->cfg.mvendorid; > return RISCV_EXCP_NONE; > @@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > static RISCVException read_marchid(CPURISCVState *env, int csrno, > target_ulong *val) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > *val = cpu->cfg.marchid; > return RISCV_EXCP_NONE; > @@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno, > static RISCVException read_mimpid(CPURISCVState *env, int csrno, > target_ulong *val) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > *val = cpu->cfg.mimpid; > return RISCV_EXCP_NONE;
On 2023/2/14 2:02, Bin Meng wrote: > Use env_archcpu() to get RISCVCPU pointer from env directly. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > target/riscv/csr.c | 36 ++++++++++++------------------------ > 1 file changed, 12 insertions(+), 24 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index da3b770894..0a3f2bef6f 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, > uint64_t bit) > { > bool virt = riscv_cpu_virt_enabled(env); > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { > return RISCV_EXCP_NONE; > @@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) > > static RISCVException vs(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); I see many RISCVCPU pointers are just for cfg in this patch. We can also use the new interface by Dianel, which will unify the interface for same function. Otherwise, Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > > if (env->misa_ext & RVV || > cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { > @@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno) > static RISCVException ctr(CPURISCVState *env, int csrno) > { > #if !defined(CONFIG_USER_ONLY) > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > int ctr_index; > target_ulong ctr_mask; > int base_csrno = CSR_CYCLE; > @@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno) > #if !defined(CONFIG_USER_ONLY) > static RISCVException mctr(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > int ctr_index; > int base_csrno = CSR_MHPMCOUNTER3; > > @@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno) > > static RISCVException sscofpmf(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_sscofpmf) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno) > > static RISCVException mstateen(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno) > > static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno) > { > bool virt = riscv_cpu_virt_enabled(env); > int index = csrno - CSR_SSTATEEN0; > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > if (!cpu->cfg.ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, > > static RISCVException sstc(CPURISCVState *env, int csrno) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > bool hmode_check = false; > > if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { > @@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno, > static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > target_ulong *val) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > *val = cpu->cfg.mvendorid; > return RISCV_EXCP_NONE; > @@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > static RISCVException read_marchid(CPURISCVState *env, int csrno, > target_ulong *val) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > *val = cpu->cfg.marchid; > return RISCV_EXCP_NONE; > @@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno, > static RISCVException read_mimpid(CPURISCVState *env, int csrno, > target_ulong *val) > { > - CPUState *cs = env_cpu(env); > - RISCVCPU *cpu = RISCV_CPU(cs); > + RISCVCPU *cpu = env_archcpu(env); > > *val = cpu->cfg.mimpid; > return RISCV_EXCP_NONE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da3b770894..0a3f2bef6f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) { bool virt = riscv_cpu_virt_enabled(env); - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { return RISCV_EXCP_NONE; @@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); if (env->misa_ext & RVV || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { @@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno) static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); int ctr_index; target_ulong ctr_mask; int base_csrno = CSR_CYCLE; @@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); int ctr_index; int base_csrno = CSR_MHPMCOUNTER3; @@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno) static RISCVException sscofpmf(CPURISCVState *env, int csrno) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); if (!cpu->cfg.ext_sscofpmf) { return RISCV_EXCP_ILLEGAL_INST; @@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno) static RISCVException mstateen(CPURISCVState *env, int csrno) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); if (!cpu->cfg.ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; @@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno) static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); if (!cpu->cfg.ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; @@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno) { bool virt = riscv_cpu_virt_enabled(env); int index = csrno - CSR_SSTATEEN0; - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); if (!cpu->cfg.ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; @@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, static RISCVException sstc(CPURISCVState *env, int csrno) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); bool hmode_check = false; if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { @@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno, target_ulong *val) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); *val = cpu->cfg.mvendorid; return RISCV_EXCP_NONE; @@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env, int csrno, static RISCVException read_marchid(CPURISCVState *env, int csrno, target_ulong *val) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); *val = cpu->cfg.marchid; return RISCV_EXCP_NONE; @@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno, static RISCVException read_mimpid(CPURISCVState *env, int csrno, target_ulong *val) { - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env); *val = cpu->cfg.mimpid; return RISCV_EXCP_NONE;
Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Bin Meng <bmeng@tinylab.org> --- target/riscv/csr.c | 36 ++++++++++++------------------------ 1 file changed, 12 insertions(+), 24 deletions(-)