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[13/18] target/riscv: Allow debugger to access seed CSR

Message ID 20230213180215.1524938-14-bmeng@tinylab.org
State New
Headers show
Series target/riscv: Various fixes to gdbstub and CSR access | expand

Commit Message

Bin Meng Feb. 14, 2023, 1:09 a.m. UTC 
At present seed CSR is not reported in the CSR XML hence gdb cannot
access it.

Fix it by addding a debugger check in its predicate() routine.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
---

 target/riscv/csr.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Weiwei Li Feb. 14, 2023, 9:18 a.m. UTC | #1 
On 2023/2/14 09:09, Bin Meng wrote:
> At present seed CSR is not reported in the CSR XML hence gdb cannot
> access it.
>
> Fix it by addding a debugger check in its predicate() routine.

typo: adding

Otherwise, Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,
Weiwei Li

>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
>   target/riscv/csr.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 515b05348b..f1075b5728 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -458,6 +458,10 @@ static RISCVException seed(CPURISCVState *env, int csrno)
>       }
>   
>   #if !defined(CONFIG_USER_ONLY)
> +    if (env->debugger) {
> +        return RISCV_EXCP_NONE;
> +    }
> +
>       /*
>        * With a CSR read-write instruction:
>        * 1) The seed CSR is always available in machine mode as normal.
LIU Zhiwei Feb. 17, 2023, 2:59 a.m. UTC | #2 
On 2023/2/14 9:09, Bin Meng wrote:
> At present seed CSR is not reported in the CSR XML hence gdb cannot
> access it.
>
> Fix it by addding a debugger check in its predicate() routine.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
>   target/riscv/csr.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 515b05348b..f1075b5728 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -458,6 +458,10 @@ static RISCVException seed(CPURISCVState *env, int csrno)
>       }
>   
>   #if !defined(CONFIG_USER_ONLY)
> +    if (env->debugger) {
> +        return RISCV_EXCP_NONE;
> +    }
> +

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

>       /*
>        * With a CSR read-write instruction:
>        * 1) The seed CSR is always available in machine mode as normal.
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 515b05348b..f1075b5728 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -458,6 +458,10 @@  static RISCVException seed(CPURISCVState *env, int csrno)
     }
 
 #if !defined(CONFIG_USER_ONLY)
+    if (env->debugger) {
+        return RISCV_EXCP_NONE;
+    }
+
     /*
      * With a CSR read-write instruction:
      * 1) The seed CSR is always available in machine mode as normal.