[v8,07/37] target/mips: Style improvements in cpu.c

Message ID	1566216496-17375-8-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:07:46 +0200 Message-Id: <1566216496-17375-8-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v8 07/37] target/mips: Style improvements in cpu.c Precedence: list Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/mips: Misc patches for 4.2 \| expand [v8,00/37] target/mips: Misc patches for 4.2 [v8,01/37] target/mips: Add support for DSPRAM [v8,02/37] target/mips: Amend CP0 WatchHi register implementation [v8,03/37] target/mips: Amend CP0 MemoryMapID register implementation [v8,04/37] target/mips: Add support for emulation of GINVT instruction [v8,05/37] target/mips: Add support for emulation of CRC32 group of instructions [v8,06/37] target/mips: Style improvements in cp0_timer.c [v8,07/37] target/mips: Style improvements in cpu.c [v8,08/37] target/mips: Style improvements in internal.h [v8,10/37] target/mips: Style improvements in helper.c [v8,11/37] target/mips: Style improvements in translate.c [v8,12/37] target/mips: Style improvements in cps.c [v8,13/37] target/mips: Style improvements in mips_fulong2e.c [v8,14/37] target/mips: Style improvements in mips_int.c [v8,15/37] target/mips: Style improvements in mips_malta.c [v8,16/37] target/mips: Style improvements in mips_mipssim.c [v8,17/37] target/mips: Clean up handling of CP0 register 0 [v8,18/37] target/mips: Clean up handling of CP0 register 1 [v8,19/37] target/mips: Clean up handling of CP0 register 2 [v8,20/37] target/mips: Clean up handling of CP0 register 5 [v8,21/37] target/mips: Clean up handling of CP0 register 6 [v8,22/37] target/mips: Clean up handling of CP0 register 7 [v8,23/37] target/mips: Clean up handling of CP0 register 8 [v8,24/37] target/mips: Clean up handling of CP0 register 10 [v8,25/37] target/mips: Clean up handling of CP0 register 11 [v8,26/37] target/mips: Clean up handling of CP0 register 12 [v8,27/37] target/mips: Clean up handling of CP0 register 15 [v8,28/37] target/mips: Clean up handling of CP0 register 16 [v8,29/37] target/mips: Clean up handling of CP0 register 17 [v8,30/37] target/mips: Clean up handling of CP0 register 20 [v8,31/37] target/mips: Clean up handling of CP0 register 23 [v8,32/37] target/mips: Clean up handling of CP0 register 24 [v8,33/37] target/mips: Clean up handling of CP0 register 26 [v8,34/37] target/mips: Clean up handling of CP0 register 30 [v8,35/37] target/mips: Clean up handling of CP0 register 31 [v8,36/37] target/mips: tests/tcg: Add optional printing of more detailed failure info [v8,37/37] target/mips: tests/tcg: Fix target configurations for MSA tests

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1566216496-17375-8-git-send-email-aleksandar.markovic@rt-rk.com

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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Date: Mon, 19 Aug 2019 14:07:46 +0200
Message-Id: <1566216496-17375-8-git-send-email-aleksandar.markovic@rt-rk.com>
In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>
References: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>
MIME-Version: 1.0
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Content-Transfer-Encoding: quoted-printable
Subject: [Qemu-devel] [PATCH v8 07/37] target/mips: Style improvements in
	cpu.c
Precedence: list
Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

target/mips: Misc patches for 4.2 | expand

Commit Message

Aleksandar Markovic Aug. 19, 2019, 12:07 p.m. UTC

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 target/mips/cpu.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 39eafaf..3ffa342 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -57,9 +57,11 @@  static bool mips_cpu_has_work(CPUState *cs)
     CPUMIPSState *env = &cpu->env;
     bool has_work = false;
 
-    /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
-       interrupts wake-up the CPU, however most of the implementations only
-       check for interrupts that can be taken. */
+    /*
+     * Prior to MIPS Release 6 it is implementation dependent if non-enabled
+     * interrupts wake-up the CPU, however most of the implementations only
+     * check for interrupts that can be taken.
+     */
     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
         cpu_mips_hw_interrupts_pending(env)) {
         if (cpu_mips_hw_interrupts_enabled(env) ||
@@ -70,8 +72,10 @@  static bool mips_cpu_has_work(CPUState *cs)
 
     /* MIPS-MT has the ability to halt the CPU.  */
     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
-        /* The QEMU model will issue an _WAKE request whenever the CPUs
-           should be woken up.  */
+        /*
+         * The QEMU model will issue an _WAKE request whenever the CPUs
+         * should be woken up.
+         */
         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
             has_work = true;
         }
@@ -112,7 +116,8 @@  static void mips_cpu_reset(CPUState *s)
 #endif
 }
 
-static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
+static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+{
     MIPSCPU *cpu = MIPS_CPU(s);
     CPUMIPSState *env = &cpu->env;

[v8,07/37] target/mips: Style improvements in cpu.c

Commit Message

Patch