[v8,22/37] target/mips: Clean up handling of CP0 register 7

Message ID	1566216496-17375-23-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:08:01 +0200 Message-Id: <1566216496-17375-23-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v8 22/37] target/mips: Clean up handling of CP0 register 7 Precedence: list Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/mips: Misc patches for 4.2 \| expand [v8,00/37] target/mips: Misc patches for 4.2 [v8,01/37] target/mips: Add support for DSPRAM [v8,02/37] target/mips: Amend CP0 WatchHi register implementation [v8,03/37] target/mips: Amend CP0 MemoryMapID register implementation [v8,04/37] target/mips: Add support for emulation of GINVT instruction [v8,05/37] target/mips: Add support for emulation of CRC32 group of instructions [v8,06/37] target/mips: Style improvements in cp0_timer.c [v8,07/37] target/mips: Style improvements in cpu.c [v8,08/37] target/mips: Style improvements in internal.h [v8,10/37] target/mips: Style improvements in helper.c [v8,11/37] target/mips: Style improvements in translate.c [v8,12/37] target/mips: Style improvements in cps.c [v8,13/37] target/mips: Style improvements in mips_fulong2e.c [v8,14/37] target/mips: Style improvements in mips_int.c [v8,15/37] target/mips: Style improvements in mips_malta.c [v8,16/37] target/mips: Style improvements in mips_mipssim.c [v8,17/37] target/mips: Clean up handling of CP0 register 0 [v8,18/37] target/mips: Clean up handling of CP0 register 1 [v8,19/37] target/mips: Clean up handling of CP0 register 2 [v8,20/37] target/mips: Clean up handling of CP0 register 5 [v8,21/37] target/mips: Clean up handling of CP0 register 6 [v8,22/37] target/mips: Clean up handling of CP0 register 7 [v8,23/37] target/mips: Clean up handling of CP0 register 8 [v8,24/37] target/mips: Clean up handling of CP0 register 10 [v8,25/37] target/mips: Clean up handling of CP0 register 11 [v8,26/37] target/mips: Clean up handling of CP0 register 12 [v8,27/37] target/mips: Clean up handling of CP0 register 15 [v8,28/37] target/mips: Clean up handling of CP0 register 16 [v8,29/37] target/mips: Clean up handling of CP0 register 17 [v8,30/37] target/mips: Clean up handling of CP0 register 20 [v8,31/37] target/mips: Clean up handling of CP0 register 23 [v8,32/37] target/mips: Clean up handling of CP0 register 24 [v8,33/37] target/mips: Clean up handling of CP0 register 26 [v8,34/37] target/mips: Clean up handling of CP0 register 30 [v8,35/37] target/mips: Clean up handling of CP0 register 31 [v8,36/37] target/mips: tests/tcg: Add optional printing of more detailed failure info [v8,37/37] target/mips: tests/tcg: Fix target configurations for MSA tests

Message ID

1566216496-17375-23-git-send-email-aleksandar.markovic@rt-rk.com

State

New

Headers

From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Date: Mon, 19 Aug 2019 14:08:01 +0200
Message-Id: <1566216496-17375-23-git-send-email-aleksandar.markovic@rt-rk.com>
In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>
References: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>
Subject: [Qemu-devel] [PATCH v8 22/37] target/mips: Clean up handling of CP0
	register 7
Precedence: list
Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

target/mips: Misc patches for 4.2 | expand

Commit Message

Aleksandar Markovic Aug. 19, 2019, 12:08 p.m. UTC

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 7.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index cdcc1cc..abbb924 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7130,7 +7130,7 @@  static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_07:
         switch (sel) {
-        case 0:
+        case CP0_REG07__HWRENA:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
             register_name = "HWREna";
@@ -7869,7 +7869,7 @@  static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_07:
         switch (sel) {
-        case 0:
+        case CP0_REG07__HWRENA:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_hwrena(cpu_env, arg);
             ctx->base.is_jmp = DISAS_STOP;
@@ -8619,7 +8619,7 @@  static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_07:
         switch (sel) {
-        case 0:
+        case CP0_REG07__HWRENA:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
             register_name = "HWREna";
@@ -9340,7 +9340,7 @@  static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_07:
         switch (sel) {
-        case 0:
+        case CP0_REG07__HWRENA:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_hwrena(cpu_env, arg);
             ctx->base.is_jmp = DISAS_STOP;

[v8,22/37] target/mips: Clean up handling of CP0 register 7

Commit Message

Patch