@@ -279,6 +279,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF0 2
+#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */
@@ -6853,26 +6853,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -7621,26 +7621,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -8373,26 +8373,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -9095,26 +9095,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";