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Apply
«
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
RISCV: support riscv vector extension 0.7.1
RISCV: support riscv vector extension 0.7.1
- - - -
-
-
-
2019-08-28
LIU Zhiwei
New
[01/11] riscv: Add RV64I instructions description
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[01/13] target/riscv: Sign extend pc for different ol
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[01/38] target/riscv: implementation-defined constant parameters
target/riscv: support packed extension v0.9.2
- - 1 -
-
-
-
2021-02-12
LIU Zhiwei
New
[02/11] riscv: Add RV64M instructions description
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[02/13] target/riscv: Extend pc for runtime pc write
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[02/38] target/riscv: Hoist vector functions
target/riscv: support packed extension v0.9.2
- - 1 -
-
-
-
2021-02-12
LIU Zhiwei
New
[03/11] riscv: Add RV64A instructions description
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[03/13] target/riscv: Ignore the pc bits above XLEN
Support UXL filed in xstatus.
- - 1 -
-
-
-
2021-11-01
LIU Zhiwei
New
[03/38] target/riscv: Fixup saturate subtract function
target/riscv: support packed extension v0.9.2
- - 2 -
-
-
-
2021-02-12
LIU Zhiwei
New
[04/11] riscv: Add RV64F instructions description
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[04/13] target/riscv: Use gdb xml according to max mxlen
Support UXL filed in xstatus.
- - 1 -
-
-
-
2021-11-01
LIU Zhiwei
New
[04/38] target/riscv: 16-bit Addition & Subtraction Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[05/11] riscv: Add RV64D instructions description
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[05/13] target/riscv: Calculate address according to ol
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[05/38] target/riscv: 8-bit Addition & Subtraction Instruction
target/riscv: support packed extension v0.9.2
1 - 1 -
-
-
-
2021-02-12
LIU Zhiwei
New
[06/11] riscv: Add RV64C instructions description
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[06/13] target/riscv: Adjust vsetvl according to ol
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[06/38] target/riscv: SIMD 16-bit Shift Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[07/11] riscv: Generate payload scripts
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[07/13] target/riscv: Ajdust vector atomic check with ol
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[07/38] target/riscv: SIMD 8-bit Shift Instructions
target/riscv: support packed extension v0.9.2
1 - 1 -
-
-
-
2021-02-12
LIU Zhiwei
New
[08/11] riscv: Add standard test case
RISC-V risu porting
- - 1 -
-
-
-
2020-07-11
LIU Zhiwei
New
[08/13] target/riscv: Fix check range for first fault only
Support UXL filed in xstatus.
- - 1 -
-
-
-
2021-11-01
LIU Zhiwei
New
[08/38] target/riscv: SIMD 16-bit Compare Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[09/11] riscv: Define riscv struct reginfo
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[09/13] target/riscv: Adjust vector address with ol
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[09/38] target/riscv: SIMD 8-bit Compare Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
[1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
- - 1 -
-
-
-
2020-08-11
LIU Zhiwei
New
[1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode
[1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode
- - - -
-
-
-
2021-05-27
LIU Zhiwei
New
[1/1] tcg/tcg-op: nonatomic_op should work with smaller memop
[1/1] tcg/tcg-op: nonatomic_op should work with smaller memop
- - - -
-
-
-
2020-07-01
LIU Zhiwei
New
[1/2] target/riscv: Quiet Coverity complains about vamo*
[1/2] target/riscv: Quiet Coverity complains about vamo*
- - 1 -
-
-
-
2020-07-21
LIU Zhiwei
New
[1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
target/riscv: fixup atomic implementation
- - - -
-
-
-
2020-06-29
LIU Zhiwei
New
[1/3] fpu/softfloat: Define operations for bfloat16
Implement blfoat16 in softfloat
- - 1 -
-
-
-
2020-08-13
LIU Zhiwei
New
[1/3] select gdb fpu xml by single or double float extension
[1/3] select gdb fpu xml by single or double float extension
- - - -
-
-
-
2020-01-10
LIU Zhiwei
New
[1/4] target/arm: Fixup special cross page case for sve continuous load/store
target/arm bug fix
- - - -
-
-
-
2020-12-07
LIU Zhiwei
New
[1/5] tcg: Add tcg_gen_vec_add{sub}16_i32
tcg: Add 32-bit vector operations
- - - -
-
-
-
2021-06-24
LIU Zhiwei
New
[1/6] target/riscv: move gen_nanbox_fpr to translate.c
target/riscv: NaN-boxing for multiple precison
- - 1 -
-
-
-
2020-06-26
LIU Zhiwei
New
[10/11] riscv: Implement payload load interfaces
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[10/13] target/riscv: Adjust scalar reg in vector with ol
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[10/38] target/riscv: SIMD 16-bit Multiply Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[11/11] riscv: Add configure script
RISC-V risu porting
- - - -
-
-
-
2020-07-11
LIU Zhiwei
New
[11/13] target/riscv: Switch context in exception return
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[11/38] target/riscv: SIMD 8-bit Multiply Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[12/13] target/riscv: Don't save pc when exception return
Support UXL filed in xstatus.
- - 1 -
-
-
-
2021-11-01
LIU Zhiwei
New
[12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[13/13] target/riscv: Enable uxl field write
Support UXL filed in xstatus.
- - - -
-
-
-
2021-11-01
LIU Zhiwei
New
[13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[14/38] target/riscv: 8-bit Unpacking Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[15/38] target/riscv: 16-bit Packing Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[2/2] target/riscv: Do amo*.w insns operate with 32 bits
target/riscv: fixup atomic implementation
- - - -
-
-
-
2020-06-29
LIU Zhiwei
New
[2/2] target/riscv: fix vector index load/store constraints
[1/2] target/riscv: Quiet Coverity complains about vamo*
- - 1 -
-
-
-
2020-07-21
LIU Zhiwei
New
[2/3] RISC-V: use FIELD macro to define tb flags
[1/3] select gdb fpu xml by single or double float extension
- - - -
-
-
-
2020-01-10
LIU Zhiwei
New
[2/3] fpu/softfloat: Define convert operations for bfloat16
Implement blfoat16 in softfloat
- - 1 -
-
-
-
2020-08-13
LIU Zhiwei
New
[2/4] target/arm: Fixup contiguous first-fault and no-fault loads
target/arm bug fix
- - - -
-
-
-
2020-12-07
LIU Zhiwei
New
[2/5] tcg: Add tcg_gen_vec_add{sub}8_i32
tcg: Add 32-bit vector operations
- - - -
-
-
-
2021-06-24
LIU Zhiwei
New
[2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions.
target/riscv: NaN-boxing for multiple precison
- - 1 -
-
-
-
2020-06-26
LIU Zhiwei
New
[20/38] target/riscv: Partial-SIMD Miscellaneous Instructions
target/riscv: support packed extension v0.9.2
1 - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[22/38] target/riscv: 64-bit Add/Subtract Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[27/38] target/riscv: 32-bit Computation Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[28/38] target/riscv: Non-SIMD Miscellaneous Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[3/3] fpu/softfloat: Define misc operations for bfloat16
Implement blfoat16 in softfloat
- - 1 -
-
-
-
2020-08-13
LIU Zhiwei
New
[3/3] remove redundant check for fpu csr read and write interface
[1/3] select gdb fpu xml by single or double float extension
- - 1 -
-
-
-
2020-01-10
LIU Zhiwei
New
[3/4] target/arm: Fixup SIMD fcmla(by element) in 4H arrangement
target/arm bug fix
- - - -
-
-
-
2020-12-07
LIU Zhiwei
New
[3/5] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32
tcg: Add 32-bit vector operations
- - - -
-
-
-
2021-06-24
LIU Zhiwei
New
[3/6] target/riscv: Check for LEGAL NaN-boxing
target/riscv: NaN-boxing for multiple precison
- - - -
-
-
-
2020-06-26
LIU Zhiwei
New
[30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[33/38] target/riscv: RV64 Only 32-bit Multiply Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[37/38] target/riscv: RV64 Only 32-bit Packing Instructions
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[38/38] target/riscv: configure and turn on packed extension from command line
target/riscv: support packed extension v0.9.2
- - - -
-
-
-
2021-02-12
LIU Zhiwei
New
[4/4] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
target/arm bug fix
- - 1 -
-
-
-
2020-12-07
LIU Zhiwei
New
[4/5] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32
tcg: Add 32-bit vector operations
- - - -
-
-
-
2021-06-24
LIU Zhiwei
New
[4/6] target/riscv: check before allocating TCG temps
target/riscv: NaN-boxing for multiple precison
- - 1 -
-
-
-
2020-06-26
LIU Zhiwei
New
[5/5] tcg: Implement tcg_gen_vec_add{sub}32_tl
tcg: Add 32-bit vector operations
- - - -
-
-
-
2021-06-24
LIU Zhiwei
New
[5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN
target/riscv: NaN-boxing for multiple precison
- - - -
-
-
-
2020-06-26
LIU Zhiwei
New
[6/6] target/riscv: clean up fmv.w.x
target/riscv: NaN-boxing for multiple precison
- - 1 -
-
-
-
2020-06-26
LIU Zhiwei
New
[RFC,01/11] target/riscv: Add CLIC CSR mintstatus
RISC-V: support clic v0.9 specification
- - - -
-
-
-
2021-04-09
LIU Zhiwei
New
[RFC,01/13] target/riscv: Add UXL to tb flags
Support UXL field in mstatus
- - 1 -
-
-
-
2021-08-05
LIU Zhiwei
New
[RFC,02/11] target/riscv: Update CSR xintthresh in CLIC mode
RISC-V: support clic v0.9 specification
- - 1 -
-
-
-
2021-04-09
LIU Zhiwei
New
[RFC,02/13] target/riscv: Support UXL32 for branch instructions
Support UXL field in mstatus
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2021-08-05
LIU Zhiwei
New
[RFC,03/11] hw/intc: Add CLIC device
RISC-V: support clic v0.9 specification
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2021-04-09
LIU Zhiwei
New
[RFC,03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store
Support UXL field in mstatus
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2021-08-05
LIU Zhiwei
New
[RFC,04/11] target/riscv: Update CSR xie in CLIC mode
RISC-V: support clic v0.9 specification
- - 1 -
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2021-04-09
LIU Zhiwei
New
[RFC,04/13] target/riscv: Support UXL32 for slit/sltiu
Support UXL field in mstatus
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-
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2021-08-05
LIU Zhiwei
New
[RFC,05/11] target/riscv: Update CSR xip in CLIC mode
RISC-V: support clic v0.9 specification
- - 1 -
-
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-
2021-04-09
LIU Zhiwei
New
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