diff mbox series

[36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions

Message ID 20210212150256.885-37-zhiwei_liu@c-sky.com
State New
Headers show
Series target/riscv: support packed extension v0.9.2 | expand

Commit Message

LIU Zhiwei Feb. 12, 2021, 3:02 p.m. UTC
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/helper.h                   |  2 ++
 target/riscv/insn32-64.decode           |  2 ++
 target/riscv/insn_trans/trans_rvp.c.inc |  3 +++
 target/riscv/packed_helper.c            | 13 +++++++++++++
 4 files changed, 20 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 85290a2b05..d3dd1fb248 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1469,4 +1469,6 @@  DEF_HELPER_4(kmsxda32, tl, env, tl, tl, tl)
 DEF_HELPER_3(smds32, tl, env, tl, tl)
 DEF_HELPER_3(smdrs32, tl, env, tl, tl)
 DEF_HELPER_3(smxds32, tl, env, tl, tl)
+
+DEF_HELPER_3(sraiw_u, tl, env, tl, tl)
 #endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index ccdd965963..32066d3ac2 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -164,3 +164,5 @@  kmsxda32   0100111  ..... ..... 010 ..... 1111111 @r
 smds32     0101100  ..... ..... 010 ..... 1111111 @r
 smdrs32    0110100  ..... ..... 010 ..... 1111111 @r
 smxds32    0111100  ..... ..... 010 ..... 1111111 @r
+
+sraiw_u    0011010  ..... ..... 001 ..... 1111111 @sh5
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index d2000bcfb5..57827d2e15 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1212,4 +1212,7 @@  GEN_RVP_R_ACC_OOL(kmsxda32);
 GEN_RVP_R_OOL(smds32);
 GEN_RVP_R_OOL(smdrs32);
 GEN_RVP_R_OOL(smxds32);
+
+/* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
+GEN_RVP_SHIFTI(sraiw_u, sraiw_u, NULL);
 #endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index bd24d5145a..69a7788e99 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3805,4 +3805,17 @@  static inline void do_smxds32(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR(smxds32, 1, sizeof(target_ulong));
+
+/* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
+static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va,
+                         void *vb, uint8_t i)
+{
+    int64_t *d = vd;
+    int32_t *a = va;
+    uint8_t shift = *(uint8_t *)vb;
+
+    *d = vssra32(env, 0, a[H4(i)], shift);
+}
+
+RVPR(sraiw_u, 1, sizeof(target_ulong));
 #endif