Show patches with: State = Action Required       |   427111 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2,25/25] docs/system: riscv: Add documentation for sifive_u machine hw/riscv: sifive_u: Add missing SPI support - - 1 - --- 2021-01-23 Bin Meng New
[v2,24/25] docs/system: Add RISC-V documentation hw/riscv: sifive_u: Add missing SPI support - - 1 - --- 2021-01-23 Bin Meng New
[v2,23/25] docs/system: Sort targets in alphabetical order hw/riscv: sifive_u: Add missing SPI support - - 1 - --- 2021-01-23 Bin Meng New
[v2,22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value hw/riscv: sifive_u: Add missing SPI support - - 1 - --- 2021-01-23 Bin Meng New
[v2,21/25] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Add missing SPI support - - 1 - --- 2021-01-23 Bin Meng New
[v2,20/25] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/riscv: sifive_u: Add missing SPI support - - 1 - --- 2021-01-23 Bin Meng New
[v2,19/25] hw/ssi: Add SiFive SPI controller support hw/riscv: sifive_u: Add missing SPI support - - - - --- 2021-01-23 Bin Meng New
[v2,18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription hw/riscv: sifive_u: Add missing SPI support - - - - --- 2021-01-23 Bin Meng New
[v2,17/25] hw/sd: ssi-sd: Support multiple block write hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,16/25] hw/sd: ssi-sd: Support single block write hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,15/25] hw/sd: Introduce receive_ready() callback hw/riscv: sifive_u: Add missing SPI support 1 - 1 - --- 2021-01-23 Bin Meng New
[v2,14/25] hw/sd: sd.h: Cosmetic change of using spaces hw/riscv: sifive_u: Add missing SPI support - - 2 - --- 2021-01-23 Bin Meng New
[v2,13/25] hw/sd: sd: Allow single/multiple block write for SPI mode hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,12/25] hw/sd: sd: Remove duplicated codes in single/multiple block read/write hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer hw/riscv: sifive_u: Add missing SPI support - - 2 - --- 2021-01-23 Bin Meng New
[v2,10/25] hw/sd: ssi-sd: Support multiple block read hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION hw/riscv: sifive_u: Add missing SPI support - 1 1 - --- 2021-01-23 Bin Meng New
[v2,08/25] hw/sd: ssi-sd: Add a state representing Nac hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,07/25] hw/sd: ssi-sd: Suffix a data block with CRC16 hw/riscv: sifive_u: Add missing SPI support 1 1 1 - --- 2021-01-23 Bin Meng New
[v2,06/25] util: Add CRC16 (CCITT) calculation routines hw/riscv: sifive_u: Add missing SPI support 1 - 1 - --- 2021-01-23 Bin Meng New
[v2,05/25] hw/sd: sd: Drop sd_crc16() hw/riscv: sifive_u: Add missing SPI support - - 2 1 --- 2021-01-23 Bin Meng New
[v2,04/25] hw/sd: sd: Support CMD59 for SPI mode hw/riscv: sifive_u: Add missing SPI support - - 2 1 --- 2021-01-23 Bin Meng New
[v2,03/25] hw/sd: ssi-sd: Fix incorrect card response sequence hw/riscv: sifive_u: Add missing SPI support - 1 2 1 --- 2021-01-23 Bin Meng New
[v2,02/25] hw/block: m25p80: Add various ISSI flash information hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,01/25] hw/block: m25p80: Add ISSI SPI flash support hw/riscv: sifive_u: Add missing SPI support - - - - --- 2021-01-23 Bin Meng New
hw/mips: loongson3: Drop 'struct MemmapEntry' hw/mips: loongson3: Drop 'struct MemmapEntry' - - 1 1 --- 2021-01-22 Bin Meng New
roms/opensbi: Upgrade from v0.8 to v0.9 roms/opensbi: Upgrade from v0.8 to v0.9 - - 1 - --- 2021-01-19 Bin Meng New
hw/misc: sifive_u_otp: Use error_report() when block operation fails hw/misc: sifive_u_otp: Use error_report() when block operation fails - - 2 - --- 2021-01-19 Bin Meng New
target/riscv: Declare csr_ops[] with a known size target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-01-19 Bin Meng New
[v2,2/2] target/riscv: Remove built-in GDB XML files for CSRs target/riscv: Generate the GDB XML file for CSR registers dynamically - - 1 - --- 2021-01-16 Bin Meng New
[v2,1/2] target/riscv: Generate the GDB XML file for CSR registers dynamically target/riscv: Generate the GDB XML file for CSR registers dynamically - - 1 - --- 2021-01-16 Bin Meng New
[9/9] hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[8/9] Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles" hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[7/9] Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command" hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[6/9] hw/ssi: xilinx_spips: Fix generic fifo dummy cycle handling hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 1 - - --- 2021-01-14 Bin Meng New
[5/9] hw/block: m25p80: Support fast read for SST flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[4/9] hw/block: m25p80: Fix the number of dummy bytes needed for Spansion flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[3/9] hw/block: m25p80: Fix the number of dummy bytes needed for Macronix flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 1 - - --- 2021-01-14 Bin Meng New
[2/9] hw/block: m25p80: Fix the number of dummy bytes needed for Numonyx/Micron flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 1 - - --- 2021-01-14 Bin Meng New
[1/9] hw/block: m25p80: Fix the number of dummy bytes needed for Windbond flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 3 - - --- 2021-01-14 Bin Meng New
[2/4] target/riscv: Add CSR name in the CSR function table target/riscv: Generate the GDB XML file for CSR registers dynamically - - 1 - --- 2021-01-12 Bin Meng New
[1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external target/riscv: Generate the GDB XML file for CSR registers dynamically - - 2 - --- 2021-01-12 Bin Meng New
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type - - 2 - --- 2021-01-09 Bin Meng New
[v3,4/4] docs/system: arm: Add sabrelite board description hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot - - 1 - --- 2021-01-06 Bin Meng New
[v3,3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6 hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot - - 1 - --- 2021-01-06 Bin Meng New
[v3,2/4] hw/msic: imx6_ccm: Correct register value for silicon type hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot - - 1 - --- 2021-01-06 Bin Meng New
[v3,1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot - - 1 - --- 2021-01-06 Bin Meng New
[v5,2/2] hw/block: m25p80: Implement AAI-WP command support for SST flashes [v5,1/2] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2020-12-23 Bin Meng New
[v5,1/2] hw/block: m25p80: Don't write to flash if write is disabled [v5,1/2] hw/block: m25p80: Don't write to flash if write is disabled - 1 2 - --- 2020-12-23 Bin Meng New
[v2,3/3] net: checksum: Introduce fine control over checksum type [v2,1/3] net: checksum: Skip fragmented IP packets - - 1 - --- 2020-12-11 Bin Meng New
[v2,2/3] net: checksum: Add IP header checksum calculation [v2,1/3] net: checksum: Skip fragmented IP packets - - - - --- 2020-12-11 Bin Meng New
[v2,1/3] net: checksum: Skip fragmented IP packets [v2,1/3] net: checksum: Skip fragmented IP packets - - - - --- 2020-12-11 Bin Meng New
hw/block: m25p80: Fix fast read for SST flashes hw/block: m25p80: Fix fast read for SST flashes 1 - - - --- 2020-11-30 Bin Meng New
[v2] target/i386: seg_helper: Correct segement selector nullification in the RET/IRET helper [v2] target/i386: seg_helper: Correct segement selector nullification in the RET/IRET helper - - - - --- 2020-11-13 Bin Meng New
[v4] hw/riscv: microchip_pfsoc: Correct DDR memory map [v4] hw/riscv: microchip_pfsoc: Correct DDR memory map - - 1 - --- 2020-11-01 Bin Meng New
hw/9pfs: virtio-9p: Ensure config space is a multiple of 4 bytes hw/9pfs: virtio-9p: Ensure config space is a multiple of 4 bytes - - - - --- 2020-10-29 Bin Meng New
[v2,10/10] hw/riscv: microchip_pfsoc: Hook the I2C1 controller hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[RESEND,6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-27 Bin Meng New
[2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - - - --- 2020-10-27 Bin Meng New
[1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - - - --- 2020-10-27 Bin Meng New
hw/sd: Fix 2 GiB card CSD register values hw/sd: Fix 2 GiB card CSD register values - 1 - 1 --- 2020-10-25 Bin Meng New
hw/sd: Zero out function selection fields before being populated hw/sd: Zero out function selection fields before being populated - 1 1 - --- 2020-10-24 Bin Meng New
[RESEND,v2] hw/intc: Move sifive_plic.h to the include directory [RESEND,v2] hw/intc: Move sifive_plic.h to the include directory - 1 1 - --- 2020-10-13 Bin Meng New
[12/12] hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[11/12] hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[10/12] hw/riscv: Always build riscv_hart.c hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[09/12] hw/riscv: Move sifive_test model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[08/12] hw/riscv: Move sifive_uart model to hw/char hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[07/12] hw/riscv: Move riscv_htif model to hw/char hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[06/12] hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[05/12] hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[04/12] hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[03/12] hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[02/12] hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[01/12] hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[v3,16/16] hw/riscv: sifive_u: Connect a DMA controller hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,11/16] hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 3 - --- 2020-09-01 Bin Meng New
[v3,10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,09/16] hw/dma: Add SiFive platform DMA controller emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support 1 - - - --- 2020-09-01 Bin Meng New
[v3,08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,07/16] hw/sd: Add Cadence SDHCI emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support 2 - - - --- 2020-09-01 Bin Meng New
[v3,06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 1 - --- 2020-09-01 Bin Meng New
[v3,03/16] target/riscv: cpu: Set reset vector based on the configured property value hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,02/16] hw/riscv: hart: Add a new 'resetvec' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support - - 2 - --- 2020-09-01 Bin Meng New
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