| Message ID | 1599129623-68957-10-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/riscv: Clean up the directory | expand |
On Thu, Sep 3, 2020 at 3:46 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > This is an effort to clean up the hw/riscv directory. Ideally it > should only contain the RISC-V SoC / machine codes plus generic > codes. Let's move sifive_test model to hw/misc directory. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > include/hw/{riscv => misc}/sifive_test.h | 0 > hw/{riscv => misc}/sifive_test.c | 2 +- > hw/riscv/virt.c | 2 +- > hw/misc/Kconfig | 3 +++ > hw/misc/meson.build | 1 + > hw/riscv/Kconfig | 1 + > hw/riscv/meson.build | 1 - > 7 files changed, 7 insertions(+), 3 deletions(-) > rename include/hw/{riscv => misc}/sifive_test.h (100%) > rename hw/{riscv => misc}/sifive_test.c (98%) > > diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h > similarity index 100% > rename from include/hw/riscv/sifive_test.h > rename to include/hw/misc/sifive_test.h > diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c > similarity index 98% > rename from hw/riscv/sifive_test.c > rename to hw/misc/sifive_test.c > index 0c78fb2..45d9399 100644 > --- a/hw/riscv/sifive_test.c > +++ b/hw/misc/sifive_test.c > @@ -25,7 +25,7 @@ > #include "qemu/module.h" > #include "sysemu/runstate.h" > #include "hw/hw.h" > -#include "hw/riscv/sifive_test.h" > +#include "hw/misc/sifive_test.h" > > static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) > { > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 0caab8e..41bd2f3 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -30,12 +30,12 @@ > #include "hw/char/serial.h" > #include "target/riscv/cpu.h" > #include "hw/riscv/riscv_hart.h" > -#include "hw/riscv/sifive_test.h" > #include "hw/riscv/virt.h" > #include "hw/riscv/boot.h" > #include "hw/riscv/numa.h" > #include "hw/intc/sifive_clint.h" > #include "hw/intc/sifive_plic.h" > +#include "hw/misc/sifive_test.h" > #include "chardev/char.h" > #include "sysemu/arch_init.h" > #include "sysemu/device_tree.h" > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig > index fa3d0f4..3185456 100644 > --- a/hw/misc/Kconfig > +++ b/hw/misc/Kconfig > @@ -134,6 +134,9 @@ config MAC_VIA > config AVR_POWER > bool > > +config SIFIVE_TEST > + bool > + > config SIFIVE_E_PRCI > bool > > diff --git a/hw/misc/meson.build b/hw/misc/meson.build > index 018a88c..bd24132 100644 > --- a/hw/misc/meson.build > +++ b/hw/misc/meson.build > @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) > softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) > > # RISC-V devices > +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) > softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) > softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) > softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c')) > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index a046157..8e07100 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -61,6 +61,7 @@ config RISCV_VIRT > select SIFIVE > select SIFIVE_CLINT > select SIFIVE_PLIC > + select SIFIVE_TEST > > config MICROCHIP_PFSOC > bool > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index da32148..3cf9380 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) > riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) > riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) > riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) > -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) > riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) > riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) > riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) > -- > 2.7.4 > >
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h similarity index 100% rename from include/hw/riscv/sifive_test.h rename to include/hw/misc/sifive_test.h diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c similarity index 98% rename from hw/riscv/sifive_test.c rename to hw/misc/sifive_test.c index 0c78fb2..45d9399 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/misc/sifive_test.c @@ -25,7 +25,7 @@ #include "qemu/module.h" #include "sysemu/runstate.h" #include "hw/hw.h" -#include "hw/riscv/sifive_test.h" +#include "hw/misc/sifive_test.h" static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0caab8e..41bd2f3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,12 +30,12 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" +#include "hw/misc/sifive_test.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fa3d0f4..3185456 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -134,6 +134,9 @@ config MAC_VIA config AVR_POWER bool +config SIFIVE_TEST + bool + config SIFIVE_E_PRCI bool diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 018a88c..bd24132 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) # RISC-V devices +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a046157..8e07100 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -61,6 +61,7 @@ config RISCV_VIRT select SIFIVE select SIFIVE_CLINT select SIFIVE_PLIC + select SIFIVE_TEST config MICROCHIP_PFSOC bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index da32148..3cf9380 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))