Show patches with: Submitter = Bin Meng       |    State = Action Required       |    Archived = No       |   134 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
riscv: virt: Allow PCI address 0 riscv: virt: Allow PCI address 0 - - 1 - 0 0 0 2019-11-22 Bin Meng New
riscv: sifive_u: Add a "serial" property for board serial number riscv: sifive_u: Add a "serial" property for board serial number - - 2 - 0 0 0 2019-11-16 Bin Meng New
[v2,2/2] riscv: sifive_u: Add ethernet0 to the aliases node [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 2 - 0 0 0 2019-09-21 Bin Meng New
[v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 1 - 0 0 0 2019-09-21 Bin Meng New
riscv: Skip checking CSR privilege level in debugger mode riscv: Skip checking CSR privilege level in debugger mode - - 1 - 0 0 0 2019-09-20 Bin Meng New
[v8,32/32] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,30/32] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,29/32] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,28/32] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,27/32] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,26/32] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,25/32] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,23/32] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,21/32] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,20/32] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,18/32] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,16/32] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,14/32] riscv: sifive_e: Drop sifive_mmio_emulate() riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,13/32] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,10/32] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,06/32] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - 0 0 0 2019-09-06 Bin Meng New
[v8,05/32] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-06 Bin Meng New
[v8,04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,03/32] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,02/32] riscv: sifive_test: Add reset functionality riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion [v8,01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion - 1 1 - 0 0 0 2019-09-06 Bin Meng New
riscv: hw: Remove duplicated "hw/hw.h" inclusion riscv: hw: Remove duplicated "hw/hw.h" inclusion - 1 - - 0 0 0 2019-09-06 Bin Meng New
[v2] riscv: sifive_test: Add reset functionality [v2] riscv: sifive_test: Add reset functionality - - 1 - 0 0 0 2019-09-05 Bin Meng New
[v7,30/30] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,28/30] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,27/30] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,26/30] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,25/30] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,24/30] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,23/30] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - 0 0 0 2019-09-01 Bin Meng New
[v7,22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,21/30] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,19/30] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,18/30] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,16/30] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,14/30] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-01 Bin Meng New
[v7,12/30] riscv: sifive_e: Drop sifive_mmio_emulate() riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,11/30] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-01 Bin Meng New
[v7,10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - 0 0 0 2019-09-01 Bin Meng New
[v7,09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-01 Bin Meng New
[v7,08/30] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,04/30] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - 0 0 0 2019-09-01 Bin Meng New
[v7,03/30] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - 0 0 0 2019-09-01 Bin Meng New
[v7,02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v7,01/30] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-09-01 Bin Meng New
[v6,30/30] riscv: sifive_u: Update model and compatible strings in device tree [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,28/30] riscv: sifive_u: Fix broken GEM support [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,27/30] riscv: sifive_u: Instantiate OTP memory with a serial number [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,26/30] riscv: sifive: Implement a model for SiFive FU540 OTP [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - - - 0 0 0 2019-08-27 Bin Meng New
[v6,25/30] riscv: roms: Update default bios for sifive_u machine [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,24/30] riscv: sifive_u: Change UART node name in device tree [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,23/30] riscv: sifive_u: Update UART base addresses and IRQs [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property 1 - 2 - 0 0 0 2019-08-27 Bin Meng New
[v6,22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,21/30] riscv: sifive_u: Add PRCI block to the SoC [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,19/30] riscv: sifive: Implement PRCI model for FU540 [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,18/30] riscv: sifive_u: Update PLIC hart topology configuration string [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,16/30] riscv: sifive_u: Set the minimum number of cpus to 2 [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - - - 0 0 0 2019-08-27 Bin Meng New
[v6,14/30] riscv: hart: Extract hart realize to a separate routine [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - 0 0 0 2019-08-27 Bin Meng New
[v6,12/30] riscv: sifive_e: Drop sifive_mmio_emulate() [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,11/30] riscv: sifive_e: prci: Update the PRCI register block size [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - 0 0 0 2019-08-27 Bin Meng New
[v6,10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property 1 - 2 - 0 0 0 2019-08-27 Bin Meng New
[v6,09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - 0 0 0 2019-08-27 Bin Meng New
[v6,08/30] riscv: sifive_u: Remove the unnecessary include of prci header [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,04/30] riscv: hw: Change create_fdt() to return void [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 3 - 0 0 0 2019-08-27 Bin Meng New
[v6,03/30] riscv: hw: Remove not needed PLIC properties in device tree [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - 0 0 0 2019-08-27 Bin Meng New
[v6,02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property [v6,01/30] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - 0 0 0 2019-08-27 Bin Meng New
[v4,28/28] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-08-19 Bin Meng New
[v4,27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-08-19 Bin Meng New
[v4,26/28] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-08-19 Bin Meng New
[v4,25/28] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - 0 0 0 2019-08-19 Bin Meng New
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