[06/12] hw/riscv: Move sifive_plic model to hw/intc

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 {include/hw/riscv => hw/intc}/sifive_plic.h | 0
 hw/{riscv => intc}/sifive_plic.c            | 2 +-
 hw/riscv/microchip_pfsoc.c                  | 2 +-
 hw/riscv/sifive_e.c                         | 2 +-
 hw/riscv/sifive_u.c                         | 2 +-
 hw/riscv/virt.c                             | 2 +-
 hw/intc/Kconfig                             | 3 +++
 hw/intc/meson.build                         | 1 +
 hw/riscv/Kconfig                            | 5 +++++
 hw/riscv/meson.build                        | 1 -
 10 files changed, 14 insertions(+), 6 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_plic model to hw/intc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  {include/hw/riscv => hw/intc}/sifive_plic.h | 0
>  hw/{riscv => intc}/sifive_plic.c            | 2 +-
>  hw/riscv/microchip_pfsoc.c                  | 2 +-
>  hw/riscv/sifive_e.c                         | 2 +-
>  hw/riscv/sifive_u.c                         | 2 +-
>  hw/riscv/virt.c                             | 2 +-
>  hw/intc/Kconfig                             | 3 +++
>  hw/intc/meson.build                         | 1 +
>  hw/riscv/Kconfig                            | 5 +++++
>  hw/riscv/meson.build                        | 1 -
>  10 files changed, 14 insertions(+), 6 deletions(-)
>  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
>  rename hw/{riscv => intc}/sifive_plic.c (99%)
>
> diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
> similarity index 100%
> rename from include/hw/riscv/sifive_plic.h
> rename to hw/intc/sifive_plic.h
> diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
> similarity index 99%
> rename from hw/riscv/sifive_plic.c
> rename to hw/intc/sifive_plic.c
> index 11ef147..af611f8 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -27,9 +27,9 @@
>  #include "hw/pci/msi.h"
>  #include "hw/boards.h"
>  #include "hw/qdev-properties.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "target/riscv/cpu.h"
>  #include "sysemu/sysemu.h"
> -#include "hw/riscv/sifive_plic.h"
>
>  #define RISCV_DEBUG_PLIC 0
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 131eea1..4627179 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 3bdb16e..0ddcf15 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,11 +39,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7187d1a..faca2e8 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,11 +46,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index bce2020..0caab8e 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f499d0f..d079540 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
>
>  config SIFIVE_CLINT
>      bool
> +
> +config SIFIVE_PLIC
> +    bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 1e20daa..3f82cc2 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
>  specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index f8bb7e7..23b7027 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -17,6 +17,7 @@ config SIFIVE_E
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> +    select SIFIVE_PLIC
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -28,6 +29,7 @@ config SIFIVE_U
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
> +    select SIFIVE_PLIC
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
> @@ -38,6 +40,7 @@ config SPIKE
>      select HTIF
>      select SIFIVE
>      select SIFIVE_CLINT
> +    select SIFIVE_PLIC
>
>  config OPENTITAN
>      bool
> @@ -58,6 +61,7 @@ config RISCV_VIRT
>      select PFLASH_CFI01
>      select SIFIVE
>      select SIFIVE_CLINT
> +    select SIFIVE_PLIC
>
>  config MICROCHIP_PFSOC
>      bool
> @@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
>      select UNIMP
>      select MCHP_PFSOC_MMUART
>      select SIFIVE_PDMA
> +    select SIFIVE_PLIC
>      select CADENCE_SDHCI
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index ea72178..535a142 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> --
> 2.7.4
>
>