Show patches with: State = Action Required       |    Archived = No       |   126642 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: Fixed ICE caused by missing operand RISC-V: Fixed ICE caused by missing operand - - - - --- 2023-09-20 Lehua Ding New
RISC-V: Fixed failed rvv combine testcases RISC-V: Fixed failed rvv combine testcases - - - - --- 2023-11-07 Lehua Ding New
RISC-V: Folding memory for FP + constant case RISC-V: Folding memory for FP + constant case - - - - --- 2023-07-12 Jivan Hakobyan New
RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions itself. RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions itself. - - - - --- 2021-04-28 Geng Qi New
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl - - - - --- 2023-08-17 Lehua Ding New
RISC-V: Force ilp32d for the T-Head FMV test RISC-V: Force ilp32d for the T-Head FMV test - - - - --- 2023-04-11 Palmer Dabbelt New
RISC-V: Generate helpers for cbranch4 RISC-V: Generate helpers for cbranch4 - - - - --- 2021-05-05 Christoph Müllner New
RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Handle combine extension in canonical ordering. RISC-V: Handle combine extension in canonical ordering. - - - - --- 2022-03-08 Liao Shihua New
RISC-V: Handle different sigcontext struct layout. RISC-V: Handle different sigcontext struct layout. - - - - --- 2022-01-18 Kito Cheng New
RISC-V: Handle extensions combination correctly in multilib-generator. RISC-V: Handle extensions combination correctly in multilib-generator. - - - - --- 2019-08-05 Kito Cheng New
RISC-V: Handle g extension in multilib-generator RISC-V: Handle g extension in multilib-generator - - - - --- 2019-08-06 Kito Cheng New
RISC-V: Handle multi-letter extension for multilib-generator RISC-V: Handle multi-letter extension for multilib-generator - - - - --- 2020-06-30 Kito Cheng New
RISC-V: Handle multi-lib path correclty for linux RISC-V: Handle multi-lib path correclty for linux - - - - --- 2023-05-04 Kito Cheng New
RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE. RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE. - - - - --- 2023-05-29 Jin Ma New
RISC-V: Handle non-legitimate address in riscv_legitimize_move RISC-V: Handle non-legitimate address in riscv_legitimize_move - - - - --- 2017-11-02 Palmer Dabbelt New
RISC-V: Handle rouding mode correctly on zfinx RISC-V: Handle rouding mode correctly on zfinx - - - - --- 2023-07-05 Kito Cheng New
RISC-V: Handle vlenb correctly in unwinding RISC-V: Handle vlenb correctly in unwinding - - - - --- 2023-02-12 Kito Cheng New
RISC-V: ICE for vlmul_ext_v intrinsic API RISC-V: ICE for vlmul_ext_v intrinsic API - - - - --- 2023-04-26 Li, Pan2 via Gcc-patches New
RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune - - - - --- 2017-11-03 Palmer Dabbelt New
RISC-V: Implement -mmemcpy-strategy= options[PR112537] RISC-V: Implement -mmemcpy-strategy= options[PR112537] - - - - --- 2023-11-17 Li Xu New
RISC-V: Implement TLS Descriptors. RISC-V: Implement TLS Descriptors. - - - - --- 2023-08-17 Tatsuyuki Ishi New
RISC-V: Implement ZACAS extensions RISC-V: Implement ZACAS extensions - - - - --- 2024-01-02 Trd thg New
RISC-V: Implement ZTSO extension. RISC-V: Implement ZTSO extension. - - - - --- 2022-03-15 Liao Shihua New
RISC-V: Implement __clear_cache via __builtin__clear_cache RISC-V: Implement __clear_cache via __builtin__clear_cache - - - - --- 2021-04-30 Palmer Dabbelt New
RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3 RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3 - - - - --- 2017-11-18 Palmer Dabbelt New
RISC-V: Implement autovec abs, vneg, vnot. RISC-V: Implement autovec abs, vneg, vnot. - - - - --- 2023-05-19 Robin Dapp New
RISC-V: Implement autovec copysign. RISC-V: Implement autovec copysign. - - - - --- 2023-06-20 Robin Dapp New
RISC-V: Implement movmemsi RISC-V: Implement movmemsi - - - - --- 2017-11-07 Palmer Dabbelt New
RISC-V: Implement movmisalign<mode> to enable SLP RISC-V: Implement movmisalign<mode> to enable SLP - - - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Implement vec_set and vec_extract. RISC-V: Implement vec_set and vec_extract. - - - - --- 2023-06-12 Robin Dapp New
RISC-V: Implement vector "average" autovec pattern. RISC-V: Implement vector "average" autovec pattern. - - - - --- 2023-08-01 Robin Dapp New
RISC-V: Implment __builtin_thread_pointer RISC-V: Implment __builtin_thread_pointer - - - - --- 2020-07-07 Kito Cheng New
RISC-V: Improve vector_insn_info::dump for LMUL and policy RISC-V: Improve vector_insn_info::dump for LMUL and policy - - - - --- 2023-05-12 Kito Cheng New
RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks. RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks. - - - - --- 2023-05-25 Jin Ma New
RISC-V: Include more registers in SIBCALL_REGS. RISC-V: Include more registers in SIBCALL_REGS. - - - - --- 2019-10-16 Jim Wilson New
RISC-V: Increase mult/div cost if not implemented in hardware. RISC-V: Increase mult/div cost if not implemented in hardware. - - - - --- 2018-01-16 Jim Wilson New
RISC-V: Increase scalar_to_vec_cost from 1 to 3 RISC-V: Increase scalar_to_vec_cost from 1 to 3 - - - - --- 2024-01-11 juzhe.zhong@rivai.ai New
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -… RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -… - - - - --- 2023-05-10 Li Xu New
RISC-V: Introduce RVV header to enable builtin types RISC-V: Introduce RVV header to enable builtin types - - - - --- 2022-09-30 juzhe.zhong@rivai.ai New
RISC-V: Introduce option -mrvv-autovec-max-lmul for RVV autovec RISC-V: Introduce option -mrvv-autovec-max-lmul for RVV autovec - - - - --- 2024-03-14 demin.han New
RISC-V: Introduce rounding mode operand into fixed-point intrinsics RISC-V: Introduce rounding mode operand into fixed-point intrinsics - - - - --- 2023-05-17 juzhe.zhong@rivai.ai New
RISC-V: Introduce vfloat16m{f}*_t and their machine mode. RISC-V: Introduce vfloat16m{f}*_t and their machine mode. - - - - --- 2023-06-01 Li, Pan2 via Gcc-patches New
RISC-V: Keep vlmax vector operators in simple form until split1 pass RISC-V: Keep vlmax vector operators in simple form until split1 pass - - - - --- 2023-09-04 Lehua Ding New
RISC-V: Legitimise the const0_rtx for RVV indexed load/store RISC-V: Legitimise the const0_rtx for RVV indexed load/store - - - - --- 2023-05-04 Li, Pan2 via Gcc-patches New
RISC-V: Legitimise the const0_rtx for RVV load/store address RISC-V: Legitimise the const0_rtx for RVV load/store address - - - - --- 2023-04-26 Li, Pan2 New
RISC-V: Libitm add RISC-V support. RISC-V: Libitm add RISC-V support. - - - - --- 2022-10-27 Xiongchuan Tan New
RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x - - - - --- 2024-01-22 juzhe.zhong@rivai.ai New
RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis - - - - --- 2023-12-22 juzhe.zhong@rivai.ai New
RISC-V: Make __divdi3 handle div by zero same as hardware. RISC-V: Make __divdi3 handle div by zero same as hardware. - - - - --- 2020-06-02 Jim Wilson New
RISC-V: Make arch-24.c to test "success" case RISC-V: Make arch-24.c to test "success" case - - - - --- 2023-08-29 Tsukasa OI New
RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL] RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL] - - - - --- 2024-01-02 juzhe.zhong@rivai.ai New
RISC-V: Make rv32i_zcmp testcase more robust RISC-V: Make rv32i_zcmp testcase more robust - - - - --- 2023-10-30 Patrick O'Neill New
RISC-V: Make stack_save_restore_2 more robust RISC-V: Make stack_save_restore_2 more robust - - - - --- 2023-10-27 Patrick O'Neill New
RISC-V: Make sure stack is always aligned during adjusting RISC-V: Make sure stack is always aligned during adjusting - - - - --- 2018-04-18 Kito Cheng New
RISC-V: Make sure we get VL REG operand for VLMAX vsetvl RISC-V: Make sure we get VL REG operand for VLMAX vsetvl - - - - --- 2023-08-30 juzhe.zhong@rivai.ai New
RISC-V: Make unique SECCAT_SRODATA names start with .srodata RISC-V: Make unique SECCAT_SRODATA names start with .srodata - - - - --- 2020-05-12 Jim Wilson New
RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering - 1 - - --- 2023-10-09 Christoph Müllner New
RISC-V: Mark fsX as call clobbered when soft-float. RISC-V: Mark fsX as call clobbered when soft-float. - - - - --- 2018-01-17 Jim Wilson New
RISC-V: Minor fix for max_point RISC-V: Minor fix for max_point - - - - --- 2024-04-02 demin.han New
RISC-V: Minor pattern name cleanup. RISC-V: Minor pattern name cleanup. - - - - --- 2018-05-16 Jim Wilson New
RISC-V: Minor tweak dynamic cost model RISC-V: Minor tweak dynamic cost model - - - - --- 2024-01-10 juzhe.zhong@rivai.ai New
RISC-V: Modify ABI-name length of vfloat16m8_t RISC-V: Modify ABI-name length of vfloat16m8_t - - - - --- 2024-01-12 Feng Wang New
RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo - - - - --- 2023-12-25 juzhe.zhong@rivai.ai New
RISC-V: Move STARTFILE_PREFIX_SPEC into target OS files. RISC-V: Move STARTFILE_PREFIX_SPEC into target OS files. - - - - --- 2019-06-06 Jim Wilson New
RISC-V: Move cond_copysign from combine pattern to autovec pattern RISC-V: Move cond_copysign from combine pattern to autovec pattern - - - - --- 2023-11-09 juzhe.zhong@rivai.ai New
RISC-V: Move function place to make it looks better. RISC-V: Move function place to make it looks better. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Move saturating add/subtract md pattern location [NFC] RISC-V: Move saturating add/subtract md pattern location [NFC] - - - - --- 2023-02-14 juzhe.zhong@rivai.ai New
RISC-V: Move vector-abi testcases into rvv/base folder RISC-V: Move vector-abi testcases into rvv/base folder - - 1 - --- 2023-08-24 Patrick O'Neill New
RISC-V: Name newly added flags in changelog RISC-V: Name newly added flags in changelog - - - - --- 2023-05-01 Patrick O'Neill New
RISC-V: No extensions for SImode min/max against safe constant RISC-V: No extensions for SImode min/max against safe constant - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Normalize SEW = 64 handling into a simplified function RISC-V: Normalize SEW = 64 handling into a simplified function - - - - --- 2023-02-15 juzhe.zhong@rivai.ai New
RISC-V: Normalize arch string in driver time RISC-V: Normalize arch string in driver time - - - - --- 2020-06-19 Kito Cheng New
RISC-V: Normalize user vsetvl intrinsics[PR112092] RISC-V: Normalize user vsetvl intrinsics[PR112092] - - - - --- 2023-11-08 juzhe.zhong@rivai.ai New
RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate - - - - --- 2022-11-18 Palmer Dabbelt New
RISC-V: Optimal RVV epilogue logic. RISC-V: Optimal RVV epilogue logic. - - - - --- 2022-11-14 Jiawei New
RISC-V: Optimise adding a (larger than simm12) constant RISC-V: Optimise adding a (larger than simm12) constant - - - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] - - - - --- 2023-09-22 Li Xu New
RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF - - - - --- 2023-12-20 juzhe.zhong@rivai.ai New
RISC-V: Optimize TARGET_XTHEADCONDMOV RISC-V: Optimize TARGET_XTHEADCONDMOV - - - - --- 2023-05-26 Die Li New
RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice - - - - --- 2023-11-17 juzhe.zhong@rivai.ai New
RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} - - - - --- 2023-06-25 juzhe.zhong@rivai.ai New
RISC-V: Optimize a special case of VLA SLP RISC-V: Optimize a special case of VLA SLP - - - - --- 2023-11-23 juzhe.zhong@rivai.ai New
RISC-V: Optimize branches testing a bit-range or a shifted immediate RISC-V: Optimize branches testing a bit-range or a shifted immediate - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize codegen of VLA SLP RISC-V: Optimize codegen of VLA SLP - - - - --- 2023-06-20 juzhe.zhong@rivai.ai New
RISC-V: Optimize combine sequence by merge approach RISC-V: Optimize combine sequence by merge approach - - - - --- 2023-11-13 juzhe.zhong@rivai.ai New
RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx - - - - --- 2023-10-18 juzhe.zhong@rivai.ai New
RISC-V: Optimize load memory data in rv64 RISC-V: Optimize load memory data in rv64 - - - - --- 2023-03-24 Feng Wang New
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Optimize min/max with SImode sources on 64-bit RISC-V: Optimize min/max with SImode sources on 64-bit - - - - --- 2022-12-28 Raphael Moreira Zinsly New
RISC-V: Optimize permutation codegen with vcompress RISC-V: Optimize permutation codegen with vcompress - - - - --- 2023-07-11 juzhe.zhong@rivai.ai New
RISC-V: Optimize reverse series index vector RISC-V: Optimize reverse series index vector - - - - --- 2023-06-02 juzhe.zhong@rivai.ai New
RISC-V: Optimize si to di zero-extend followed by left shift. RISC-V: Optimize si to di zero-extend followed by left shift. - - - - --- 2020-05-31 Jim Wilson New
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize the MASK opt generation RISC-V: Optimize the MASK opt generation - - - - --- 2023-03-01 Feng Wang New
RISC-V: Optimize the code gen of VLM/VSM. RISC-V: Optimize the code gen of VLM/VSM. - - - - --- 2023-02-11 Li, Pan2 via Gcc-patches New
RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization - - - - --- 2023-05-13 juzhe.zhong@rivai.ai New
RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] - - - - --- 2023-05-06 juzhe.zhong@rivai.ai New
RISC-V: Optimize zbb ins sext.b and sext.h in rv64 RISC-V: Optimize zbb ins sext.b and sext.h in rv64 - - - - --- 2023-03-24 Feng Wang New
RISC-V: Optimized for strided load/store with stride == element width[PR111450] RISC-V: Optimized for strided load/store with stride == element width[PR111450] - - - - --- 2023-09-21 Li Xu New
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