Show patches with: State = Action Required       |   127166 patches
« 1 2 ... 299 300 301 … 1271 1272 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: Add Types to Un-Typed Vector Instructions: RISC-V: Add Types to Un-Typed Vector Instructions: - - - - --- 2023-08-28 Edwin Lu New
RISC-V: Add VECTOR_ALIGNMENT_REACHABLE && BUILTIN_VECTORIZATION_COST target hook to optimize RVV VL… RISC-V: Add VECTOR_ALIGNMENT_REACHABLE && BUILTIN_VECTORIZATION_COST target hook to optimize RVV VL… - - - - --- 2023-05-15 juzhe.zhong@rivai.ai New
RISC-V: Add VLS conditional patterns support RISC-V: Add VLS conditional patterns support - - - - --- 2023-09-22 juzhe.zhong@rivai.ai New
RISC-V: Add VLS mask modes mov patterns[PR111311] RISC-V: Add VLS mask modes mov patterns[PR111311] - - - - --- 2023-09-07 juzhe.zhong@rivai.ai New
RISC-V: Add VLS modes VEC_PERM support[PR111311] RISC-V: Add VLS modes VEC_PERM support[PR111311] - - - - --- 2023-09-09 juzhe.zhong@rivai.ai New
RISC-V: Add VLS modes for GNU vectors RISC-V: Add VLS modes for GNU vectors - - - - --- 2023-06-18 juzhe.zhong@rivai.ai New
RISC-V: Add VLS to mask vec_extract [PR114668]. RISC-V: Add VLS to mask vec_extract [PR114668]. - - - - --- 2024-04-15 Robin Dapp New
RISC-V: Add VSETVL testcases for indexed loads/stores. RISC-V: Add VSETVL testcases for indexed loads/stores. - - - - --- 2023-01-29 juzhe.zhong@rivai.ai New
RISC-V: Add Vector cost model framework for RVV RISC-V: Add Vector cost model framework for RVV - - - - --- 2023-08-31 juzhe.zhong@rivai.ai New
RISC-V: Add Veyron V1 pipeline description RISC-V: Add Veyron V1 pipeline description - - - - --- 2023-06-07 Raphael Moreira Zinsly New
RISC-V: Add XiangShan Nanhu microarchitecture. RISC-V: Add XiangShan Nanhu microarchitecture. - - - - --- 2024-02-27 Jiawei New
RISC-V: Add Z*inx incompatible check in gcc. RISC-V: Add Z*inx incompatible check in gcc. - - - - --- 2023-03-26 Jiawei New
RISC-V: Add ZVFH extension to the -march= option RISC-V: Add ZVFH extension to the -march= option - - - - --- 2023-05-31 Li, Pan2 via Gcc-patches New
RISC-V: Add ZVFHMIN autovec block testcase RISC-V: Add ZVFHMIN autovec block testcase - - - - --- 2023-06-12 juzhe.zhong@rivai.ai New
RISC-V: Add ZVFHMIN extension to the -march= option RISC-V: Add ZVFHMIN extension to the -march= option - - - - --- 2023-05-25 Li, Pan2 via Gcc-patches New
RISC-V: Add Zawrs ISA extension support RISC-V: Add Zawrs ISA extension support - - - - --- 2022-10-27 Christoph Müllner New
RISC-V: Add Zvfbfmin extension to the -march= option RISC-V: Add Zvfbfmin extension to the -march= option - - 1 - --- 2023-12-13 Xiao Zeng New
RISC-V: Add __RISCV_ prefix to VXRM and FRM enum RISC-V: Add __RISCV_ prefix to VXRM and FRM enum - - - - --- 2023-06-01 juzhe.zhong@rivai.ai New
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid - - - - --- 2023-06-02 juzhe.zhong@rivai.ai New
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid - - - - --- 2023-06-01 juzhe.zhong@rivai.ai New
RISC-V: Add all mask C++ api tests RISC-V: Add all mask C++ api tests - - - - --- 2023-02-16 juzhe.zhong@rivai.ai New
RISC-V: Add an experimental vector calling convention RISC-V: Add an experimental vector calling convention - - - - --- 2023-06-25 Lehua Ding New
RISC-V: Add and document the "-mno-relax" option RISC-V: Add and document the "-mno-relax" option - - - - --- 2018-03-01 Palmer Dabbelt New
RISC-V: Add attribute to vtype change only vsetvl RISC-V: Add attribute to vtype change only vsetvl - - - - --- 2023-08-23 juzhe.zhong@rivai.ai New
RISC-V: Add attributes for VSETVL PASS RISC-V: Add attributes for VSETVL PASS - - - - --- 2022-11-28 juzhe.zhong@rivai.ai New
RISC-V: Add autovec FP binary operations. RISC-V: Add autovec FP binary operations. - - - - --- 2023-06-14 Robin Dapp New
RISC-V: Add autovec FP int->float conversion. RISC-V: Add autovec FP int->float conversion. - - - - --- 2023-06-26 Robin Dapp New
RISC-V: Add autovec FP unary operations. RISC-V: Add autovec FP unary operations. - - - - --- 2023-06-14 Robin Dapp New
RISC-V: Add autovec FP widening/narrowing. RISC-V: Add autovec FP widening/narrowing. - - - - --- 2023-06-26 Robin Dapp New
RISC-V: Add autovec sign/zero extension and truncation. RISC-V: Add autovec sign/zero extension and truncation. - - - - --- 2023-05-25 Robin Dapp New
RISC-V: Add autovect widening/narrowing Integer/FP conversions. RISC-V: Add autovect widening/narrowing Integer/FP conversions. - - - - --- 2023-06-26 Robin Dapp New
RISC-V: Add avail interface into function_group_info RISC-V: Add avail interface into function_group_info - - - - --- 2023-12-07 Feng Wang New
RISC-V: Add available vector size for RVV RISC-V: Add available vector size for RVV - - - - --- 2023-10-09 juzhe.zhong@rivai.ai New
RISC-V: Add basic vec_init support for RVV auto-vectorizaiton RISC-V: Add basic vec_init support for RVV auto-vectorizaiton - - - - --- 2023-05-10 juzhe.zhong@rivai.ai New
RISC-V: Add bext pattern for ZBS RISC-V: Add bext pattern for ZBS - - - - --- 2023-05-04 Raphael Moreira Zinsly New
RISC-V: Add binary op vx constraint tests RISC-V: Add binary op vx constraint tests - - - - --- 2023-02-03 juzhe.zhong@rivai.ai New
RISC-V: Add binary vx C/C++ support RISC-V: Add binary vx C/C++ support - - - - --- 2023-02-03 juzhe.zhong@rivai.ai New
RISC-V: Add binop constraint tests RISC-V: Add binop constraint tests - - - - --- 2023-01-31 juzhe.zhong@rivai.ai New
RISC-V: Add binop constraints tests for integer compare RISC-V: Add binop constraints tests for integer compare - - - - --- 2023-02-13 juzhe.zhong@rivai.ai New
RISC-V: Add blocker for gather/scatter auto-vectorization RISC-V: Add blocker for gather/scatter auto-vectorization - - - - --- 2023-12-05 juzhe.zhong@rivai.ai New
RISC-V: Add builtin .def file dependencies RISC-V: Add builtin .def file dependencies - - - - --- 2023-09-19 Tsukasa OI New
RISC-V: Add check for types without insn reservations RISC-V: Add check for types without insn reservations - - - - --- 2023-11-01 Edwin Lu New
RISC-V: Add combine optimization by slideup for vec_init vectorization RISC-V: Add combine optimization by slideup for vec_init vectorization - - - - --- 2023-11-10 juzhe.zhong@rivai.ai New
RISC-V: Add comments of some functions RISC-V: Add comments of some functions - - - - --- 2023-06-13 juzhe.zhong@rivai.ai New
RISC-V: Add conditional autovec convert(INT<->FP) patterns RISC-V: Add conditional autovec convert(INT<->FP) patterns - - - - --- 2023-08-24 Lehua Ding New
RISC-V: Add conditional convert autovec patterns between FPs RISC-V: Add conditional convert autovec patterns between FPs - - - - --- 2023-08-23 Lehua Ding New
RISC-V: Add conditional sign/zero extension and truncation autovec patterns RISC-V: Add conditional sign/zero extension and truncation autovec patterns - - - - --- 2023-08-23 Lehua Ding New
RISC-V: Add conditional sqrt autovec pattern RISC-V: Add conditional sqrt autovec pattern - - - - --- 2023-09-04 Lehua Ding New
RISC-V: Add conditional unary neg/abs/not autovec patterns RISC-V: Add conditional unary neg/abs/not autovec patterns - - - - --- 2023-08-22 Lehua Ding New
RISC-V: Add configure option: --with-multilib-config to flexible config multi-lib settings. RISC-V: Add configure option: --with-multilib-config to flexible config multi-lib settings. - - - - --- 2020-10-16 Kito Cheng New
RISC-V: Add constraint tests RISC-V: Add constraint tests - - - - --- 2023-02-07 juzhe.zhong@rivai.ai New
RISC-V: Add crypto machine descriptions RISC-V: Add crypto machine descriptions - - - - --- 2023-12-22 Feng Wang New
RISC-V: Add csrr vlenb instruction. RISC-V: Add csrr vlenb instruction. - - - - --- 2022-08-30 juzhe.zhong@rivai.ai New
RISC-V: Add custom RTEMS multilibs RISC-V: Add custom RTEMS multilibs - - - - --- 2018-06-14 Sebastian Huber New
RISC-V: Add divmod instruction support RISC-V: Add divmod instruction support - - - - --- 2023-02-17 Matevos Mehrabyan New
RISC-V: Add duplicate vector support. RISC-V: Add duplicate vector support. - - - - --- 2022-11-25 juzhe.zhong@rivai.ai New
RISC-V: Add dynamic LMUL compile option RISC-V: Add dynamic LMUL compile option - - - - --- 2023-08-31 juzhe.zhong@rivai.ai New
RISC-V: Add early continue for ENTRY and EXIT block RISC-V: Add early continue for ENTRY and EXIT block - - - - --- 2023-08-25 juzhe.zhong@rivai.ai New
RISC-V: Add explicit braces to eliminate warning. RISC-V: Add explicit braces to eliminate warning. - - - - --- 2023-11-29 Li Xu New
RISC-V: Add fault first load C/C++ support RISC-V: Add fault first load C/C++ support - - - - --- 2023-03-07 juzhe.zhong@rivai.ai New
RISC-V: Add fixed PR111255 testcase by other patch RISC-V: Add fixed PR111255 testcase by other patch - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Add fixed-point support RISC-V: Add fixed-point support - - - - --- 2023-02-10 juzhe.zhong@rivai.ai New
RISC-V: Add floating-point RVV C/C++ api RISC-V: Add floating-point RVV C/C++ api - - - - --- 2023-02-17 juzhe.zhong@rivai.ai New
RISC-V: Add floating-point to integer conversion RVV auto-vectorization support RISC-V: Add floating-point to integer conversion RVV auto-vectorization support - - - - --- 2023-05-29 juzhe.zhong@rivai.ai New
RISC-V: Add function comment for cleanup_insns. RISC-V: Add function comment for cleanup_insns. - - - - --- 2023-04-23 juzhe.zhong@rivai.ai New
RISC-V: Add h extension support RISC-V: Add h extension support - - - - --- 2022-10-24 Kito Cheng New
RISC-V: Add has compatible check for conflict vsetvl fusion RISC-V: Add has compatible check for conflict vsetvl fusion - - - - --- 2024-01-17 juzhe.zhong@rivai.ai New
RISC-V: Add implementation for builtin overflow RISC-V: Add implementation for builtin overflow - - - - --- 2021-01-21 Levy Hsu New
RISC-V: Add indexed loads/stores C/C++ intrinsic support RISC-V: Add indexed loads/stores C/C++ intrinsic support - - - - --- 2023-01-29 juzhe.zhong@rivai.ai New
RISC-V: Add indexed loads/stores constraints testcases RISC-V: Add indexed loads/stores constraints testcases - - - - --- 2023-01-29 juzhe.zhong@rivai.ai New
RISC-V: Add initial cost handling for segment loads/stores. RISC-V: Add initial cost handling for segment loads/stores. - - - - --- 2024-02-26 Robin Dapp New
RISC-V: Add initial pipeline description for an out-of-order core. RISC-V: Add initial pipeline description for an out-of-order core. - - - - --- 2023-08-23 Robin Dapp New
RISC-V: Add integer binary vv C/C++ API support RISC-V: Add integer binary vv C/C++ API support - - - - --- 2023-01-31 juzhe.zhong@rivai.ai New
RISC-V: Add integer compare C/C++ intrinsic support RISC-V: Add integer compare C/C++ intrinsic support - - - - --- 2023-02-13 juzhe.zhong@rivai.ai New
RISC-V: Add integer widening instructions RISC-V: Add integer widening instructions - - - - --- 2023-02-07 juzhe.zhong@rivai.ai New
RISC-V: Add interrupt attribute modes. RISC-V: Add interrupt attribute modes. - - - - --- 2018-06-06 Jim Wilson New
RISC-V: Add interrupt attribute support. RISC-V: Add interrupt attribute support. - - - - --- 2018-05-25 Jim Wilson New
RISC-V: Add local user vsetvl instruction elimination RISC-V: Add local user vsetvl instruction elimination - - - - --- 2023-04-07 juzhe.zhong@rivai.ai New
RISC-V: Add macro for ilp32e ABI. Cleanup white space. RISC-V: Add macro for ilp32e ABI. Cleanup white space. - - - - --- 2018-10-03 Jim Wilson New
RISC-V: Add minimal support for 7 new unprivileged extensions RISC-V: Add minimal support for 7 new unprivileged extensions - - - - --- 2024-02-01 Monk Chiang New
RISC-V: Add missed cond autovec testcases RISC-V: Add missed cond autovec testcases - - - - --- 2023-09-12 Lehua Ding New
RISC-V: Add missing modes to the iterators RISC-V: Add missing modes to the iterators - - - - --- 2023-08-10 juzhe.zhong@rivai.ai New
RISC-V: Add missing negate patterns. RISC-V: Add missing negate patterns. - - - - --- 2018-09-26 Jim Wilson New
RISC-V: Add missing torture-init and torture-finish for rvv.exp RISC-V: Add missing torture-init and torture-finish for rvv.exp - - - - --- 2023-05-22 Kito Cheng New
RISC-V: Add missing vsetvl instruction type. RISC-V: Add missing vsetvl instruction type. - - - - --- 2022-10-10 juzhe.zhong@rivai.ai New
RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions - - - - --- 2023-05-17 juzhe.zhong@rivai.ai New
RISC-V: Add more SLP tests RISC-V: Add more SLP tests - - - - --- 2023-06-13 juzhe.zhong@rivai.ai New
RISC-V: Add naked function support. RISC-V: Add naked function support. - - - - --- 2018-01-10 Jim Wilson New
RISC-V: Add new line at end of file. RISC-V: Add new line at end of file. - - - - --- 2022-10-12 juzhe.zhong@rivai.ai New
RISC-V: Add new option -march=help to print all supported extensions RISC-V: Add new option -march=help to print all supported extensions - - 1 - --- 2024-02-15 Kito Cheng New
RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590] - - - - --- 2023-09-26 juzhe.zhong@rivai.ai New
RISC-V: Add patterns to convert AND mask to two shifts. RISC-V: Add patterns to convert AND mask to two shifts. - - - - --- 2018-06-30 Jim Wilson New
RISC-V: Add permutation C/C++ support RISC-V: Add permutation C/C++ support - - - - --- 2023-02-27 juzhe.zhong@rivai.ai New
RISC-V: Add popcount fallback expander. RISC-V: Add popcount fallback expander. - - - - --- 2023-10-18 Robin Dapp New
RISC-V: Add probability model of each block to prevent endless loop of Phase 3 RISC-V: Add probability model of each block to prevent endless loop of Phase 3 - - - - --- 2023-01-09 juzhe.zhong@rivai.ai New
RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations - - - - --- 2023-06-01 juzhe.zhong@rivai.ai New
RISC-V: Add rawmemchr expander. RISC-V: Add rawmemchr expander. - - - - --- 2023-10-26 Robin Dapp New
RISC-V: Add regression test for vsetvl bug pr113429 RISC-V: Add regression test for vsetvl bug pr113429 - - - - --- 2024-01-24 Patrick O'Neill New
RISC-V: Add require-effective-target to pr113429 testcase RISC-V: Add require-effective-target to pr113429 testcase - - - - --- 2024-01-27 Patrick O'Neill New
RISC-V: Add required tls to read thread pointer test RISC-V: Add required tls to read thread pointer test - - - - --- 2023-04-27 Li, Pan2 New
« 1 2 ... 299 300 301 … 1271 1272 »