Message ID | 1517996690-26848-6-git-send-email-patrice.chotard@st.com |
---|---|
State | Accepted |
Commit | cd389c03f270636e581a16ba157e37b47ae75d93 |
Delegated to: | Tom Rini |
Headers | show |
Series | Add DM timer support for STM32 SoCs family | expand |
On Wed, Feb 07, 2018 at 10:44:49AM +0100, patrice.chotard@st.com wrote: > From: Patrice Chotard <patrice.chotard@st.com> > > Add missing timer node to enable timer5 for STM32F7 SoCs family > > Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 9a9e4e5f3718..4a677192a2dd 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,3 +1,11 @@ +/{ + soc { + timer5: timer@40000c00 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pinctrl { usart1_pins_a: usart1@0 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 46d148eab2c8..8c6fa133e0ab 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -323,6 +323,13 @@ pinctrl-names = "default", "opendrain"; max-frequency = <48000000>; }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + }; }; };