diff mbox series

[U-Boot,4/6] clk: clk_stm32h7: Fix prescaler for Domain 3

Message ID 1517996690-26848-5-git-send-email-patrice.chotard@st.com
State Accepted
Commit 09b335a6753f5c6ad418ca5eb0cdc599857272cc
Delegated to: Tom Rini
Headers show
Series Add DM timer support for STM32 SoCs family | expand

Commit Message

Patrice CHOTARD Feb. 7, 2018, 9:44 a.m. UTC 
From: Patrice Chotard <patrice.chotard@st.com>

d1cfgr register was used to calculate the domain 3
prescaler value instead of d3cfgr.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/clk/clk_stm32h7.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Tom Rini March 14, 2018, 2:08 p.m. UTC | #1 
On Wed, Feb 07, 2018 at 10:44:48AM +0100, patrice.chotard@st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> d1cfgr register was used to calculate the domain 3
> prescaler value instead of d3cfgr.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 92db71431e45..9ee2e2e999a2 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -635,7 +635,7 @@  static ulong stm32_clk_get_rate(struct clk *clk)
 	struct stm32_rcc_regs *regs = priv->rcc_base;
 	ulong sysclk = 0;
 	u32 gate_offset;
-	u32 d1cfgr;
+	u32 d1cfgr, d3cfgr;
 	/* prescaler table lookups for clock computation */
 	u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
 	u8 source, idx;
@@ -712,9 +712,10 @@  static ulong stm32_clk_get_rate(struct clk *clk)
 		break;
 
 	case RCC_APB4ENR:
-		if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
+		d3cfgr = readl(&regs->d3cfgr);
+		if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
 			/* get D3 domain APB4 prescaler */
-			idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
+			idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
 			      RCC_D3CFGR_D3PPRE_SHIFT;
 			sysclk = sysclk / prescaler_table[idx];
 		}