From patchwork Wed Feb 7 09:44:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870286 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zbxNy202jz9s71 for ; Wed, 7 Feb 2018 20:49:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0297AC21E3B; Wed, 7 Feb 2018 09:46:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6C2C7C21E1D; Wed, 7 Feb 2018 09:45:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7EB0C21DA1; Wed, 7 Feb 2018 09:45:06 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 1EB77C21DD9 for ; Wed, 7 Feb 2018 09:45:03 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w179hel3016632; Wed, 7 Feb 2018 10:45:02 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fya265ha9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 07 Feb 2018 10:45:02 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9B2D03D; Wed, 7 Feb 2018 09:45:01 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 80F684F1C; Wed, 7 Feb 2018 09:45:01 +0000 (GMT) Received: from localhost (10.75.127.50) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 7 Feb 2018 10:45:01 +0100 From: To: , , , Date: Wed, 7 Feb 2018 10:44:49 +0100 Message-ID: <1517996690-26848-6-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517996690-26848-1-git-send-email-patrice.chotard@st.com> References: <1517996690-26848-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG8NODE3.st.com (10.75.127.24) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-07_02:, , signatures=0 Subject: [U-Boot] [PATCH 5/6] ARM: dts: stm32: Add timer support for STM32F7 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Add missing timer node to enable timer5 for STM32F7 SoCs family Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32f7-u-boot.dtsi | 8 ++++++++ arch/arm/dts/stm32f746.dtsi | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 9a9e4e5f3718..4a677192a2dd 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,3 +1,11 @@ +/{ + soc { + timer5: timer@40000c00 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pinctrl { usart1_pins_a: usart1@0 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 46d148eab2c8..8c6fa133e0ab 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -323,6 +323,13 @@ pinctrl-names = "default", "opendrain"; max-frequency = <48000000>; }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + }; }; };