| Message ID | 20190821080942.13724-2-uboot@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Support Andes RISC-V l2cache on AE350 platform | expand |
Hi Rick, On Wed, Aug 21, 2019 at 4:15 PM Andes <uboot@andestech.com> wrote: > > From: Rick Chen <rick@andestech.com> > > The L2 cache will be enabled in init flow of dm cache > driver when it detect L2 node in dtb. > > When U-Boot jumps to Linux Kernel, the disable ops will > be called to flush and disable the L2 cache via the dm > cache driver. > The commit message should be rewritten. It's just about adding cache enable/disable ops to the DM cache uclass driver. No need to mention whether it's L1 or L2 cache, jumping to Linux, etc. > Signed-off-by: Rick Chen <rick@andestech.com> > Cc: KC Lin <kclin@andestech.com> > --- > drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++ > include/cache.h | 31 +++++++++++++++++++++++++++++++ > 2 files changed, 51 insertions(+) > Other than above, Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Regards, Bin
Hi Bin > Hi Rick, > > On Wed, Aug 21, 2019 at 4:15 PM Andes <uboot@andestech.com> wrote: > > > > From: Rick Chen <rick@andestech.com> > > > > The L2 cache will be enabled in init flow of dm cache > > driver when it detect L2 node in dtb. > > > > When U-Boot jumps to Linux Kernel, the disable ops will > > be called to flush and disable the L2 cache via the dm > > cache driver. > > > > The commit message should be rewritten. It's just about adding cache > enable/disable ops to the DM cache uclass driver. No need to mention > whether it's L1 or L2 cache, jumping to Linux, etc. I will rewrite the commit message. Thanks for reviewing. Regards, Rick > > > Signed-off-by: Rick Chen <rick@andestech.com> > > Cc: KC Lin <kclin@andestech.com> > > --- > > drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++ > > include/cache.h | 31 +++++++++++++++++++++++++++++++ > > 2 files changed, 51 insertions(+) > > > > Other than above, > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > Regards, > Bin
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c index 97ce024..3b20a10 100644 --- a/drivers/cache/cache-uclass.c +++ b/drivers/cache/cache-uclass.c @@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info) return ops->get_info(dev, info); } +int cache_enable(struct udevice *dev) +{ + struct cache_ops *ops = cache_get_ops(dev); + + if (!ops->enable) + return -ENOSYS; + + return ops->enable(dev); +} + +int cache_disable(struct udevice *dev) +{ + struct cache_ops *ops = cache_get_ops(dev); + + if (!ops->disable) + return -ENOSYS; + + return ops->disable(dev); +} + UCLASS_DRIVER(cache) = { .id = UCLASS_CACHE, .name = "cache", diff --git a/include/cache.h b/include/cache.h index c6334ca..32f59fd 100644 --- a/include/cache.h +++ b/include/cache.h @@ -22,6 +22,22 @@ struct cache_ops { * @return 0 if OK, -ve on error */ int (*get_info)(struct udevice *dev, struct cache_info *info); + + /** + * enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev); + + /** + * disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*disable)(struct udevice *dev); }; #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) @@ -35,4 +51,19 @@ struct cache_ops { */ int cache_get_info(struct udevice *dev, struct cache_info *info); +/** + * cache_enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_enable(struct udevice *dev); + +/** + * cache_disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_disable(struct udevice *dev); #endif