From patchwork Wed Aug 21 08:09:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1150674 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46D0qb0M6Jz9sN4 for ; Wed, 21 Aug 2019 18:16:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 510DEC21FCC; Wed, 21 Aug 2019 08:16:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3EA41C21FC8; Wed, 21 Aug 2019 08:16:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F0BFFC21FB1; Wed, 21 Aug 2019 08:16:01 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 82430C21C2C for ; Wed, 21 Aug 2019 08:15:58 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x7L83bDJ095882; Wed, 21 Aug 2019 16:03:37 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Wed, 21 Aug 2019 16:15:35 +0800 From: Andes To: Date: Wed, 21 Aug 2019 16:09:35 +0800 Message-ID: <20190821080942.13724-2-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190821080942.13724-1-uboot@andestech.com> References: <20190821080942.13724-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x7L83bDJ095882 Cc: rickchen36@gmail.com, kclin@andestech.com Subject: [U-Boot] [PATCH v3 1/8] dm: cache: Add enable and disable ops for cache uclass X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen The L2 cache will be enabled in init flow of dm cache driver when it detect L2 node in dtb. When U-Boot jumps to Linux Kernel, the disable ops will be called to flush and disable the L2 cache via the dm cache driver. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++ include/cache.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c index 97ce024..3b20a10 100644 --- a/drivers/cache/cache-uclass.c +++ b/drivers/cache/cache-uclass.c @@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info) return ops->get_info(dev, info); } +int cache_enable(struct udevice *dev) +{ + struct cache_ops *ops = cache_get_ops(dev); + + if (!ops->enable) + return -ENOSYS; + + return ops->enable(dev); +} + +int cache_disable(struct udevice *dev) +{ + struct cache_ops *ops = cache_get_ops(dev); + + if (!ops->disable) + return -ENOSYS; + + return ops->disable(dev); +} + UCLASS_DRIVER(cache) = { .id = UCLASS_CACHE, .name = "cache", diff --git a/include/cache.h b/include/cache.h index c6334ca..32f59fd 100644 --- a/include/cache.h +++ b/include/cache.h @@ -22,6 +22,22 @@ struct cache_ops { * @return 0 if OK, -ve on error */ int (*get_info)(struct udevice *dev, struct cache_info *info); + + /** + * enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev); + + /** + * disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*disable)(struct udevice *dev); }; #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) @@ -35,4 +51,19 @@ struct cache_ops { */ int cache_get_info(struct udevice *dev, struct cache_info *info); +/** + * cache_enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_enable(struct udevice *dev); + +/** + * cache_disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_disable(struct udevice *dev); #endif