diff mbox series

[U-Boot,4/6] riscv: cache: Flush L2 cache before jump to linux

Message ID 20190528093914.4672-5-uboot@andestech.com
State Superseded
Delegated to: Andes
Headers show
Series Support Andes RISC-V l2cache on AE350 platform | expand

Commit Message

Andes May 28, 2019, 9:39 a.m. UTC 
From: Rick Chen <rick@andestech.com>

Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 arch/riscv/cpu/ax25/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Bin Meng June 4, 2019, 2:48 a.m. UTC | #1 
Hi Rick,

On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Flush and disable cache in cleanup_before_linux()
> which will be called before jump to linux.
>
> The sequence will be preferred as below:
> L1 flush -> L1 disable -> L2 flush -> L2 disable
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  arch/riscv/cpu/ax25/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> index 76689b2..9e7579a 100644
> --- a/arch/riscv/cpu/ax25/cpu.c
> +++ b/arch/riscv/cpu/ax25/cpu.c
> @@ -7,6 +7,7 @@
>  /* CPU specific code */
>  #include <common.h>
>  #include <asm/cache.h>
> +#include <asm/v5l2cache.h>
>
>  /*
>   * cleanup_before_linux() is called just before we call linux
> @@ -22,6 +23,9 @@ int cleanup_before_linux(void)
>         cache_flush();
>         icache_disable();
>         dcache_disable();
> +#ifdef CONFIG_RISCV_NDS_CACHE
> +       v5l2_disable();
> +#endif

The direct call into a driver should be avoided. Instead, use a proper
DM cache uclass driver API (see my review comments in patch [1/6])

Regards,
Bin
Rick Chen June 5, 2019, 9:24 a.m. UTC | #2 
Hi Bin

>
> Hi Rick,
>
> On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Flush and disable cache in cleanup_before_linux()
> > which will be called before jump to linux.
> >
> > The sequence will be preferred as below:
> > L1 flush -> L1 disable -> L2 flush -> L2 disable
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  arch/riscv/cpu/ax25/cpu.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> > index 76689b2..9e7579a 100644
> > --- a/arch/riscv/cpu/ax25/cpu.c
> > +++ b/arch/riscv/cpu/ax25/cpu.c
> > @@ -7,6 +7,7 @@
> >  /* CPU specific code */
> >  #include <common.h>
> >  #include <asm/cache.h>
> > +#include <asm/v5l2cache.h>
> >
> >  /*
> >   * cleanup_before_linux() is called just before we call linux
> > @@ -22,6 +23,9 @@ int cleanup_before_linux(void)
> >         cache_flush();
> >         icache_disable();
> >         dcache_disable();
> > +#ifdef CONFIG_RISCV_NDS_CACHE
> > +       v5l2_disable();
> > +#endif
>
> The direct call into a driver should be avoided. Instead, use a proper
> DM cache uclass driver API (see my review comments in patch [1/6])

OK
I will use DM cache uclass driver API to disable L2 driver.

Thanks
Rick

>
> Regards,
> Bin
diff mbox series

Patch

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..9e7579a 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,7 @@ 
 /* CPU specific code */
 #include <common.h>
 #include <asm/cache.h>
+#include <asm/v5l2cache.h>
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -22,6 +23,9 @@  int cleanup_before_linux(void)
 	cache_flush();
 	icache_disable();
 	dcache_disable();
+#ifdef CONFIG_RISCV_NDS_CACHE
+	v5l2_disable();
+#endif
 
 	return 0;
 }