From patchwork Tue May 28 09:39:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1106197 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Cppy66l3z9s4V for ; Tue, 28 May 2019 19:44:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 7DF93C2209F; Tue, 28 May 2019 09:44:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2B132C220DE; Tue, 28 May 2019 09:44:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DDF49C21C3F; Tue, 28 May 2019 09:44:22 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 22669C21C29 for ; Tue, 28 May 2019 09:44:21 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x4S9cdBe083360; Tue, 28 May 2019 17:38:39 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 28 May 2019 17:43:56 +0800 From: Andes To: Date: Tue, 28 May 2019 17:39:09 +0800 Message-ID: <20190528093914.4672-2-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x4S9cdBe083360 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 1/6] dm: cache: add v5l2 cache controller driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/include/asm/global_data.h | 3 ++ arch/riscv/include/asm/v5l2cache.h | 61 +++++++++++++++++++++ drivers/cache/Kconfig | 9 ++++ drivers/cache/Makefile | 1 + drivers/cache/cache-v5l2.c | 102 +++++++++++++++++++++++++++++++++++ 5 files changed, 176 insertions(+) create mode 100644 arch/riscv/include/asm/v5l2cache.h create mode 100644 drivers/cache/cache-v5l2.c diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b74bd7e..6e52d5d 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,6 +24,9 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif +#ifdef CONFIG_V5L2_CACHE + void __iomem *v5l2; /* v5l2 base address */ +#endif #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif diff --git a/arch/riscv/include/asm/v5l2cache.h b/arch/riscv/include/asm/v5l2cache.h new file mode 100644 index 0000000..8ed1c6c --- /dev/null +++ b/arch/riscv/include/asm/v5l2cache.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#ifndef _ASM_V5_L2CACHE_H +#define _ASM_V5_L2CACHE_H + +struct l2cache { + volatile u64 configure; + volatile u64 control; + volatile u64 hpm0; + volatile u64 hpm1; + volatile u64 hpm2; + volatile u64 hpm3; + volatile u64 error_status; + volatile u64 ecc_error; + volatile u64 cctl_command0; + volatile u64 cctl_access_line0; + volatile u64 cctl_command1; + volatile u64 cctl_access_line1; + volatile u64 cctl_command2; + volatile u64 cctl_access_line2; + volatile u64 cctl_command3; + volatile u64 cctl_access_line4; + volatile u64 cctl_status; +}; + +/* Control Register */ +#define L2_ENABLE 0x1 +/* prefetch */ +#define IPREPETCH_OFF 3 +#define DPREPETCH_OFF 5 +#define IPREPETCH_MSK (3 << IPREPETCH_OFF) +#define DPREPETCH_MSK (3 << DPREPETCH_OFF) +/* tag ram */ +#define TRAMOCTL_OFF 8 +#define TRAMICTL_OFF 10 +#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF) +#define TRAMICTL_MSK BIT(TRAMICTL_OFF) +/* data ram */ +#define DRAMOCTL_OFF 11 +#define DRAMICTL_OFF 13 +#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF) +#define DRAMICTL_MSK BIT(DRAMICTL_OFF) + +/* CCTL Command Register */ +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10) +#define L2_WBINVAL_ALL 0x12 + +/* CCTL Status Register */ +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4)) +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4)) +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4)) +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4)) + +void v5l2_enable(void); +void v5l2_disable(void); + +#endif /* _ASM_V5_L2CACHE_H */ diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 24def7a..665689a 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -22,4 +22,13 @@ config L2X0_CACHE ARMv7(32-bit) devices. The driver configures the cache settings found in the device tree. +config V5L2_CACHE + tristate "Andes V5L2 cache driver" + select CACHE + depends on RISCV_NDS_CACHE + help + Support Andes V5L2 cache controller in AE350 platform. + It will configure tag and data ram timing control from the + device tree and enable L2 cache. + endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 9deb961..4a6458c 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o +obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c new file mode 100644 index 0000000..7022feb --- /dev/null +++ b/drivers/cache/cache-v5l2.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void v5l2_enable(void) +{ + struct l2cache *regs = gd->arch.v5l2; + + if (regs) + setbits_le32(®s->control, L2_ENABLE); +} + +void v5l2_disable(void) +{ + volatile struct l2cache *regs = gd->arch.v5l2; + u8 hart = gd->arch.boot_hart; + void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(gd->arch.v5l2, hart); + + if ((regs) && (readl(®s->control) & L2_ENABLE)) { + writel(L2_WBINVAL_ALL, cctlcmd); + + while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) { + if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) { + printf("L2 flush illegal! hanging..."); + hang(); + } + } + clrbits_le32(®s->control, L2_ENABLE); + } +} + +static void v5l2_of_parse_and_init(struct udevice *dev) +{ + struct l2cache *regs; + u32 ctl_val, prefetch; + u32 tram_ctl[2]; + u32 dram_ctl[2]; + + regs = (struct l2cache *)dev_read_addr(dev); + gd->arch.v5l2 = regs; + ctl_val = readl(®s->control); + + if (!(ctl_val & L2_ENABLE)) + ctl_val |= L2_ENABLE; + + /* Instruction and data fetch prefetch depth */ + if (!dev_read_u32(dev, "andes,inst-prefetch", &prefetch)) { + ctl_val &= ~(IPREPETCH_MSK); + ctl_val |= (prefetch << IPREPETCH_OFF); + } + + if (!dev_read_u32(dev, "andes,data-prefetch", &prefetch)) { + ctl_val &= ~(DPREPETCH_MSK); + ctl_val |= (prefetch << DPREPETCH_OFF); + } + + /* Set tag RAM and data RAM setup and output cycle */ + if (!dev_read_u32_array(dev, "andes,tag-ram-ctl", tram_ctl, 2)) { + ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK); + ctl_val |= tram_ctl[0] << TRAMOCTL_OFF; + ctl_val |= tram_ctl[1] << TRAMICTL_OFF; + } + + if (!dev_read_u32_array(dev, "andes,data-ram-ctl", dram_ctl, 2)) { + ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK); + ctl_val |= dram_ctl[0] << DRAMOCTL_OFF; + ctl_val |= dram_ctl[1] << DRAMICTL_OFF; + } + + writel(ctl_val, ®s->control); +} + +static int v5l2_probe(struct udevice *dev) +{ + v5l2_of_parse_and_init(dev); + + return 0; +} + +static const struct udevice_id v5l2_cache_ids[] = { + { .compatible = "cache" }, + {} +}; + +U_BOOT_DRIVER(v5l2_cache) = { + .name = "v5l2_cache", + .id = UCLASS_CACHE, + .of_match = v5l2_cache_ids, + .probe = v5l2_probe, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue May 28 09:39:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1106198 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Cpqv5r07z9s4V for ; Tue, 28 May 2019 19:45:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 439ADC220FD; Tue, 28 May 2019 09:44:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A9D29C220EC; Tue, 28 May 2019 09:44:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EFFE5C21E6C; Tue, 28 May 2019 09:44:35 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 5DC1CC220DD for ; Tue, 28 May 2019 09:44:31 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x4S9cn21083380; Tue, 28 May 2019 17:38:49 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 28 May 2019 17:44:06 +0800 From: Andes To: Date: Tue, 28 May 2019 17:39:10 +0800 Message-ID: <20190528093914.4672-3-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x4S9cn21083380 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 2/6] riscv: ae350: use the v5l2 driver to configure the cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/ax25-ae350.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 3d65ce7..686ec4a 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -93,10 +94,24 @@ int smc_init(void) return 0; } +int v5l2_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); + + if (ret) + return ret; + + return 0; +} + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { smc_init(); + v5l2_init(); return 0; } From patchwork Tue May 28 09:39:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1106199 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Cpr85DpNz9s4V for ; Tue, 28 May 2019 19:46:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 624D3C220DC; Tue, 28 May 2019 09:45:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 998DBC220B8; Tue, 28 May 2019 09:45:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 46A14C220DE; Tue, 28 May 2019 09:44:43 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id D6DCEC220D7 for ; Tue, 28 May 2019 09:44:39 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x4S9cxPY083398; Tue, 28 May 2019 17:38:59 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 28 May 2019 17:44:17 +0800 From: Andes To: Date: Tue, 28 May 2019 17:39:11 +0800 Message-ID: <20190528093914.4672-4-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x4S9cxPY083398 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Select the v5l2 UCLASS_CACHE driver for AE350. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 5e682b6..dd299d9 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ax25-ae350/Kconfig @@ -25,5 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select RISCV_NDS imply SMP + imply V5L2_CACHE endif From patchwork Tue May 28 09:39:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1106202 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Cpsv5zt7z9s4V for ; Tue, 28 May 2019 19:47:31 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 82889C220B8; Tue, 28 May 2019 09:45:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 72ED0C220D7; Tue, 28 May 2019 09:45:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 20BB4C220CF; Tue, 28 May 2019 09:44:53 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 7BDEBC2209F for ; Tue, 28 May 2019 09:44:49 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x4S9d90t083459; Tue, 28 May 2019 17:39:09 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 28 May 2019 17:44:27 +0800 From: Andes To: Date: Tue, 28 May 2019 17:39:12 +0800 Message-ID: <20190528093914.4672-5-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x4S9d90t083459 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 4/6] riscv: cache: Flush L2 cache before jump to linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Flush and disable cache in cleanup_before_linux() which will be called before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/ax25/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index 76689b2..9e7579a 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -7,6 +7,7 @@ /* CPU specific code */ #include #include +#include /* * cleanup_before_linux() is called just before we call linux @@ -22,6 +23,9 @@ int cleanup_before_linux(void) cache_flush(); icache_disable(); dcache_disable(); +#ifdef CONFIG_RISCV_NDS_CACHE + v5l2_disable(); +#endif return 0; } From patchwork Tue May 28 09:39:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1106200 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Cpry4kTWz9s4V for ; Tue, 28 May 2019 19:46:42 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 52523C220F3; Tue, 28 May 2019 09:46:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D91B1C22101; Tue, 28 May 2019 09:46:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 869B0C2207A; Tue, 28 May 2019 09:45:03 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 6330FC21E3E for ; Tue, 28 May 2019 09:45:00 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x4S9dJj4083506; Tue, 28 May 2019 17:39:19 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 28 May 2019 17:44:37 +0800 From: Andes To: Date: Tue, 28 May 2019 17:39:13 +0800 Message-ID: <20190528093914.4672-6-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x4S9dJj4083506 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350_32.dts | 17 +++++++++++------ arch/riscv/dts/ae350_64.dts | 17 +++++++++++------ 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index cb6ee13..83abfcb 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0xe0500000 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + // The value format is + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 705491a..7009bdc 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + // The value format is + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { From patchwork Tue May 28 09:39:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1106201 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Cps75WF1z9s4V for ; Tue, 28 May 2019 19:46:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 7A908C2209F; Tue, 28 May 2019 09:45:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4EEA0C220DE; Tue, 28 May 2019 09:45:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7B0AEC22075; Tue, 28 May 2019 09:45:10 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 51160C220DD for ; Tue, 28 May 2019 09:45:09 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x4S9dT30083547; Tue, 28 May 2019 17:39:29 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 28 May 2019 17:44:47 +0800 From: Andes To: Date: Tue, 28 May 2019 17:39:14 +0800 Message-ID: <20190528093914.4672-7-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x4S9dT30083547 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 228fc55..d30071e 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -5,17 +5,21 @@ */ #include +#include + +#ifdef CONFIG_RISCV_NDS_CACHE +/* mcctlcommand */ +#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc + +/* D-cache operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* - * Andes' AX25 does not have a coherence agent. U-Boot must use data - * cache flush and invalidate functions to keep data in the system - * coherent. - * The implementation of the fence instruction in the AX25 flushes the - * data cache and is used for this purpose. - */ - asm volatile ("fence" ::: "memory"); +#ifdef CONFIG_RISCV_NDS_CACHE + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); +#endif } void flush_dcache_range(unsigned long start, unsigned long end) @@ -72,8 +76,8 @@ void dcache_disable(void) { #ifndef CONFIG_SYS_DCACHE_OFF #ifdef CONFIG_RISCV_NDS_CACHE + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( - "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t"