diff mbox series

[U-Boot,5/6] riscv: dts: move out AE350 L2 node from cpus node

Message ID 20190528093914.4672-6-uboot@andestech.com
State Superseded
Delegated to: Andes
Headers show
Series Support Andes RISC-V l2cache on AE350 platform | expand

Commit Message

Andes May 28, 2019, 9:39 a.m. UTC 
From: Rick Chen <rick@andestech.com>

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
 arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
 2 files changed, 22 insertions(+), 12 deletions(-)

Comments

Bin Meng June 4, 2019, 2:48 a.m. UTC | #1 
Hi Rick,

On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> When L2 node exists inside cpus node, uclass_get_device
> can not parse L2 node successfully. So move it outside
> from cpus node.
>
> Also add tag-ram-ctl and data-ram-ctl attributes for
> v5l2 cache controller driver. This can adjust timing
> by requirement from dtb to improve performance.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
>  arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
>  2 files changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> index cb6ee13..83abfcb 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -62,13 +62,18 @@
>                                 compatible = "riscv,cpu-intc";
>                         };
>                 };
> +       };
>
> -               L2: l2-cache@e0500000 {
> -                       compatible = "cache";
> -                       cache-level = <2>;
> -                       cache-size = <0x40000>;
> -                       reg = <0x0 0xe0500000 0x0 0x40000>;
> -               };
> +       L2: l2-cache@e0500000 {
> +               compatible = "cache";

too generic compatible string (see my previous comments in patch [1/6])

> +               cache-level = <2>;
> +               cache-size = <0x40000>;
> +               reg = <0xe0500000 0x40000>;
> +               andes,inst-prefetch = <3>;
> +               andes,data-prefetch = <3>;
> +               // The value format is <XRAMOCTL XRAMICTL>

nits: no //, use /* */

> +               andes,tag-ram-ctl = <0 0>;
> +               andes,data-ram-ctl = <0 0>;
>         };
>
>         memory@0 {
> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> index 705491a..7009bdc 100644
> --- a/arch/riscv/dts/ae350_64.dts
> +++ b/arch/riscv/dts/ae350_64.dts
> @@ -62,13 +62,18 @@
>                                 compatible = "riscv,cpu-intc";
>                         };
>                 };
> +       };
>
> -               L2: l2-cache@e0500000 {
> -                       compatible = "cache";
> -                       cache-level = <2>;
> -                       cache-size = <0x40000>;
> -                       reg = <0x0 0xe0500000 0x0 0x40000>;
> -               };
> +       L2: l2-cache@e0500000 {
> +               compatible = "cache";
> +               cache-level = <2>;
> +               cache-size = <0x40000>;
> +               reg = <0x0 0xe0500000 0x0 0x40000>;
> +               andes,inst-prefetch = <3>;
> +               andes,data-prefetch = <3>;
> +               // The value format is <XRAMOCTL XRAMICTL>

nits: no //, use /* */

> +               andes,tag-ram-ctl = <0 0>;
> +               andes,data-ram-ctl = <0 0>;
>         };
>
>         memory@0 {
> --

Regards,
Bin
Rick Chen June 5, 2019, 9:33 a.m. UTC | #2 
Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年6月4日 週二 上午10:48寫道：
>
> Hi Rick,
>
> On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > When L2 node exists inside cpus node, uclass_get_device
> > can not parse L2 node successfully. So move it outside
> > from cpus node.
> >
> > Also add tag-ram-ctl and data-ram-ctl attributes for
> > v5l2 cache controller driver. This can adjust timing
> > by requirement from dtb to improve performance.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
> >  arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
> >  2 files changed, 22 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > index cb6ee13..83abfcb 100644
> > --- a/arch/riscv/dts/ae350_32.dts
> > +++ b/arch/riscv/dts/ae350_32.dts
> > @@ -62,13 +62,18 @@
> >                                 compatible = "riscv,cpu-intc";
> >                         };
> >                 };
> > +       };
> >
> > -               L2: l2-cache@e0500000 {
> > -                       compatible = "cache";
> > -                       cache-level = <2>;
> > -                       cache-size = <0x40000>;
> > -                       reg = <0x0 0xe0500000 0x0 0x40000>;
> > -               };
> > +       L2: l2-cache@e0500000 {
> > +               compatible = "cache";
>
> too generic compatible string (see my previous comments in patch [1/6])

Same replying  in patch [1/6]
>
> > +               cache-level = <2>;
> > +               cache-size = <0x40000>;
> > +               reg = <0xe0500000 0x40000>;
> > +               andes,inst-prefetch = <3>;
> > +               andes,data-prefetch = <3>;
> > +               // The value format is <XRAMOCTL XRAMICTL>
>
> nits: no //, use /* */

OK
I will use /* */ instead of //

>
> > +               andes,tag-ram-ctl = <0 0>;
> > +               andes,data-ram-ctl = <0 0>;
> >         };
> >
> >         memory@0 {
> > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> > index 705491a..7009bdc 100644
> > --- a/arch/riscv/dts/ae350_64.dts
> > +++ b/arch/riscv/dts/ae350_64.dts
> > @@ -62,13 +62,18 @@
> >                                 compatible = "riscv,cpu-intc";
> >                         };
> >                 };
> > +       };
> >
> > -               L2: l2-cache@e0500000 {
> > -                       compatible = "cache";
> > -                       cache-level = <2>;
> > -                       cache-size = <0x40000>;
> > -                       reg = <0x0 0xe0500000 0x0 0x40000>;
> > -               };
> > +       L2: l2-cache@e0500000 {
> > +               compatible = "cache";
> > +               cache-level = <2>;
> > +               cache-size = <0x40000>;
> > +               reg = <0x0 0xe0500000 0x0 0x40000>;
> > +               andes,inst-prefetch = <3>;
> > +               andes,data-prefetch = <3>;
> > +               // The value format is <XRAMOCTL XRAMICTL>
>
> nits: no //, use /* */

I will use /* */ instead of //

Thanks
Rick

>
> > +               andes,tag-ram-ctl = <0 0>;
> > +               andes,data-ram-ctl = <0 0>;
> >         };
> >
> >         memory@0 {
> > --
>
> Regards,
> Bin
diff mbox series

Patch

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..83abfcb 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@ 
 				compatible = "riscv,cpu-intc";
 			};
 		};
+	};
 
-		L2: l2-cache@e0500000 {
-			compatible = "cache";
-			cache-level = <2>;
-			cache-size = <0x40000>;
-			reg = <0x0 0xe0500000 0x0 0x40000>;
-		};
+	L2: l2-cache@e0500000 {
+		compatible = "cache";
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		reg = <0xe0500000 0x40000>;
+		andes,inst-prefetch = <3>;
+		andes,data-prefetch = <3>;
+		// The value format is <XRAMOCTL XRAMICTL>
+		andes,tag-ram-ctl = <0 0>;
+		andes,data-ram-ctl = <0 0>;
 	};
 
 	memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..7009bdc 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@ 
 				compatible = "riscv,cpu-intc";
 			};
 		};
+	};
 
-		L2: l2-cache@e0500000 {
-			compatible = "cache";
-			cache-level = <2>;
-			cache-size = <0x40000>;
-			reg = <0x0 0xe0500000 0x0 0x40000>;
-		};
+	L2: l2-cache@e0500000 {
+		compatible = "cache";
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		reg = <0x0 0xe0500000 0x0 0x40000>;
+		andes,inst-prefetch = <3>;
+		andes,data-prefetch = <3>;
+		// The value format is <XRAMOCTL XRAMICTL>
+		andes,tag-ram-ctl = <0 0>;
+		andes,data-ram-ctl = <0 0>;
 	};
 
 	memory@0 {