| Message ID | 1405686582-28356-2-git-send-email-pekon@ti.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Tom Rini |
| Headers | show |
On Fri, Jul 18, 2014 at 05:59:40PM +0530, pekon gupta wrote: > Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 > ARM: omap: merge GPMC initialization code for all platform > > 1) NAND device are not directly memory-mapped to CPU address-space, they are > indirectly accessed via following GPMC registers: > - GPMC_NAND_COMMAND_x > - GPMC_NAND_ADDRESS_x > - GPMC_NAND_DATA_x > Therefore from CPU's point of view, NAND address-map can be limited to just > above register addresses. But GPMC chip-select address-map can be configured > in granularity of 16MB only. > So this patch uses GPMC_SIZE_16M for all NAND devices. > > 2) NOR device are directly memory-mapped to CPU address-space, so its > address-map size depends on actual addressable region in NOR FLASH device. > So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map > size configuration. > > Signed-off-by: Pekon Gupta <pekon@ti.com> Applied to u-boot-ti/master, thanks!
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 5bc7e1f..05b81e0 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -87,8 +87,13 @@ void gpmc_init(void) STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; - u32 size = GPMC_SIZE_16M; u32 base = CONFIG_SYS_FLASH_BASE; + u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + /* min 16MB */ GPMC_SIZE_16M))); + #elif defined(CONFIG_NAND) /* configure GPMC for NAND */ const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -99,8 +104,9 @@ void gpmc_init(void) M_NAND_GPMC_CONFIG6, 0 }; - u32 size = GPMC_SIZE_256M; u32 base = CONFIG_SYS_NAND_BASE; + u32 size = GPMC_SIZE_16M; + #elif defined(CONFIG_CMD_ONENAND) const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, ONENAND_GPMC_CONFIG2, diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a48b386..c1a6ada 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -453,6 +453,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Reduce SPL size by removing unlikey targets */ #ifdef CONFIG_NOR_BOOT
Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta <pekon@ti.com> --- arch/arm/cpu/armv7/omap-common/mem-common.c | 10 ++++++++-- include/configs/am335x_evm.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-)