From patchwork Fri Jul 18 12:29:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 371516 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 47B88140090 for ; Fri, 18 Jul 2014 22:33:56 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3EDA8A73FB; Fri, 18 Jul 2014 14:33:32 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EZE85iDWKmky; Fri, 18 Jul 2014 14:33:32 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 17D15A7467; Fri, 18 Jul 2014 14:33:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DD8B0A73F2 for ; Fri, 18 Jul 2014 14:33:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UVSIYqQ9KbyO for ; Fri, 18 Jul 2014 14:33:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 9E961A73E9 for ; Fri, 18 Jul 2014 14:32:56 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6ICWqwd016563 for ; Fri, 18 Jul 2014 07:32:54 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6ICWqrf023033 for ; Fri, 18 Jul 2014 07:32:52 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Fri, 18 Jul 2014 07:32:51 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6ICWm0s000619; Fri, 18 Jul 2014 07:32:51 -0500 From: Pekon Gupta To: Tom Rini Date: Fri, 18 Jul 2014 17:59:40 +0530 Message-ID: <1405686582-28356-2-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.5.1.163.gd7aced9 In-Reply-To: <1405686582-28356-1-git-send-email-pekon@ti.com> References: <1405686582-28356-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v1 1/3] ARM: omap: fix GPMC address-map size for NAND and NOR devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta --- arch/arm/cpu/armv7/omap-common/mem-common.c | 10 ++++++++-- include/configs/am335x_evm.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 5bc7e1f..05b81e0 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -87,8 +87,13 @@ void gpmc_init(void) STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; - u32 size = GPMC_SIZE_16M; u32 base = CONFIG_SYS_FLASH_BASE; + u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + /* min 16MB */ GPMC_SIZE_16M))); + #elif defined(CONFIG_NAND) /* configure GPMC for NAND */ const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -99,8 +104,9 @@ void gpmc_init(void) M_NAND_GPMC_CONFIG6, 0 }; - u32 size = GPMC_SIZE_256M; u32 base = CONFIG_SYS_NAND_BASE; + u32 size = GPMC_SIZE_16M; + #elif defined(CONFIG_CMD_ONENAND) const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, ONENAND_GPMC_CONFIG2, diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a48b386..c1a6ada 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -453,6 +453,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Reduce SPL size by removing unlikey targets */ #ifdef CONFIG_NOR_BOOT