| Message ID | 1380010799-26820-1-git-send-email-Po.Liu@freescale.com |
|---|---|
| State | Changes Requested |
| Delegated to: | York Sun |
| Headers | show |
On Tue, 2013-09-24 at 16:19 +0800, Po Liu wrote: > c29xpcie REV_A board DDR ECC chip has bad impedance in hardware, > force that kind of board to be DDR ECC off when booting. > Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on > in uboot enviroment. Why does the Rev A workaround require setting the default ECC to off for other revisions? Why are you removing the use of CONFIG_DEF_HWCONFIG? -Scott
On Tue, 2013-09-24 at 22:19 -0500, Liu Po-B43644 wrote: > Hi Wood Scott, > > 1. Do you mean it is better to set the hwconfig=fsl_ddr:ecc=on as default setting? > 2. Do you mean keep the CONFIG_DEF_HWCONFIG define as below is better? > > #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on > "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" Yes to both. There's no reason to change this just because one board revision can't do ECC (which is handled elsewhere). -Scott
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index b017cfd..4077ed9 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -9,6 +9,9 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> +#include "cpld.h" + +#define C29XPCIE_HARDWARE_REVA 0x40 /* * Micron MT41J128M16HA-15E * */ @@ -61,7 +64,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); int i; + popts->clk_adjust = 2; popts->cpo_override = 0x1f; popts->write_data_delay = 4; @@ -79,6 +84,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->trwt_override = 1; popts->trwt = 0; + if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) + popts->ecc_mode = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..877375d 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -432,7 +432,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ + "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "loadaddr=1000000\0" \
c29xpcie REV_A board DDR ECC chip has bad impedance in hardware, force that kind of board to be DDR ECC off when booting. Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on in uboot enviroment. Signed-off-by: Po Liu <Po.Liu@freescale.com> --- Add this patch after the camelcase patch http://patchwork.ozlabs.org/patch/271670/ was added. board/freescale/c29xpcie/ddr.c | 8 ++++++++ include/configs/C29XPCIE.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-)